// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Applied Micro X-Gene SoC Ethernet v2 Driver
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*
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* Copyright (c) 2017, Applied Micro Circuits Corporation
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* Author(s): Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*/
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#include "main.h"
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/* create circular linked list of descriptors */
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void xge_setup_desc(struct xge_desc_ring *ring)
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{
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struct xge_raw_desc *raw_desc;
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dma_addr_t dma_h, next_dma;
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u16 offset;
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int i;
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for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
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raw_desc = &ring->raw_desc[i];
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offset = (i + 1) & (XGENE_ENET_NUM_DESC - 1);
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next_dma = ring->dma_addr + (offset * XGENE_ENET_DESC_SIZE);
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raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
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SET_BITS(PKT_SIZE, SLOT_EMPTY));
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dma_h = upper_32_bits(next_dma);
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raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) |
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SET_BITS(NEXT_DESC_ADDRH, dma_h));
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}
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}
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void xge_update_tx_desc_addr(struct xge_pdata *pdata)
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{
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struct xge_desc_ring *ring = pdata->tx_ring;
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dma_addr_t dma_addr = ring->dma_addr;
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xge_wr_csr(pdata, DMATXDESCL, dma_addr);
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xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr));
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ring->head = 0;
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ring->tail = 0;
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}
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void xge_update_rx_desc_addr(struct xge_pdata *pdata)
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{
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struct xge_desc_ring *ring = pdata->rx_ring;
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dma_addr_t dma_addr = ring->dma_addr;
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xge_wr_csr(pdata, DMARXDESCL, dma_addr);
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xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr));
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ring->head = 0;
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ring->tail = 0;
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}
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void xge_intr_enable(struct xge_pdata *pdata)
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{
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u32 data;
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data = RX_PKT_RCVD | TX_PKT_SENT;
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xge_wr_csr(pdata, DMAINTRMASK, data);
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}
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void xge_intr_disable(struct xge_pdata *pdata)
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{
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xge_wr_csr(pdata, DMAINTRMASK, 0);
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}
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