// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include "rk628.h"
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#include "rk628_cru.h"
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#include "rk628_dsi.h"
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#include "rk628_mipi_dphy.h"
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#include "rk628_combtxphy.h"
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enum {
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VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
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VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
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VID_MODE_TYPE_BURST,
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};
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#define MIPI_DSI_MODE_VIDEO BIT(0)
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#define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
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#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
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#define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
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#define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
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#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
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#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
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#define MIPI_DSI_MODE_LPM BIT(11)
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static inline int dsi_write(struct rk628 *rk628, int id, u32 reg, u32 val)
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{
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unsigned int dsi_base;
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dsi_base = id ? DSI1_BASE : DSI0_BASE;
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return rk628_i2c_write(rk628, dsi_base + reg, val);
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}
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static inline int dsi_read(struct rk628 *rk628, int id, u32 reg, u32 *val)
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{
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unsigned int dsi_base;
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dsi_base = id ? DSI1_BASE : DSI0_BASE;
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return rk628_i2c_read(rk628, dsi_base + reg, val);
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}
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static inline int dsi_update_bits(struct rk628 *rk628, int id,
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u32 reg, u32 mask, u32 val)
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{
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unsigned int dsi_base;
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dsi_base = id ? DSI1_BASE : DSI0_BASE;
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return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);
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}
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static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi)
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{
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int dev_id;
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unsigned int dsi_base;
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unsigned int val, mask;
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int ret;
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struct rk628 *rk628 = dsi->rk628;
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dev_id = RK628_DEV_DSI0;
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dsi_base = DSI0_BASE;
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, 0);
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testif_testclr_assert(dsi->rk628);
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/* Set all REQUEST inputs to zero */
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
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FORCETXSTOPMODE(0) | FORCERXMODE(0));
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udelay(1);
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testif_testclr_deassert(dsi->rk628);
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mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps);
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
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PHY_ENABLECLK, PHY_ENABLECLK);
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
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PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
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dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
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usleep_range(1500, 2000);
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rk628_txphy_power_on(rk628);
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ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
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dsi_base + DSI_PHY_STATUS,
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val, val & PHY_LOCK, 0, 1000);
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if (ret < 0)
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dev_err(rk628->dev, "PHY is not locked\n");
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usleep_range(100, 200);
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mask = PHY_STOPSTATELANE;
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ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
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dsi_base + DSI_PHY_STATUS,
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val, (val & mask) == mask,
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0, 1000);
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if (ret < 0)
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dev_err(rk628->dev, "lane module is not in stop state\n");
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udelay(10);
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}
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static void rk628_dsi_pre_enable(struct rk628_dsi *dsi)
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{
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u32 val;
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struct rk628 *rk628 = dsi->rk628;
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u32 lane_mbps = dsi->lane_mbps;
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dsi_write(rk628, 0, DSI_PWR_UP, RESET);
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dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
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val = DIV_ROUND_UP(lane_mbps >> 3, 20);
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dsi_write(rk628, 0, DSI_CLKMGR_CFG,
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TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
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val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
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if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
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val &= ~EOTP_TX_EN;
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dsi_write(rk628, 0, DSI_PCKHDL_CFG, val);
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dsi_write(rk628, 0, DSI_TO_CNT_CFG,
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HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
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dsi_write(rk628, 0, DSI_BTA_TO_CNT, 0xd00);
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dsi_write(rk628, 0, DSI_PHY_TMR_CFG,
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PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
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MAX_RD_TIME(10000));
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dsi_write(rk628, 0, DSI_PHY_TMR_LPCLK_CFG,
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PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
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dsi_write(rk628, 0, DSI_PHY_IF_CFG,
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PHY_STOP_WAIT_TIME(0x20) | N_LANES(4 - 1));
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mipi_dphy_power_on_dsi(dsi);
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dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
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}
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static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
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{
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unsigned int lanebyteclk = (dsi->lane_mbps * 1000L) >> 3;
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u64 dpipclk;
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u32 hline, hs, hbp, hline_time, hs_time, hbp_time;
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u32 vactive, vs, vfp, vbp;
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u32 val;
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int pkt_size;
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struct v4l2_bt_timings *bt = &dsi->timings.bt;
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struct rk628 *rk628 = dsi->rk628;
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dpipclk = bt->pixelclock;
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do_div(dpipclk, 1000);
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val = LP_HFP_EN | LP_HBP_EN | LP_VACT_EN | LP_VFP_EN | LP_VBP_EN |
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LP_VSA_EN;
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if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
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val &= ~LP_HFP_EN;
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if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
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val &= ~LP_HBP_EN;
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if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
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val |= VID_MODE_TYPE_BURST;
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else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
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val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
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else
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val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
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dsi_write(rk628, 0, DSI_VID_MODE_CFG, val);
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if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
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dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
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AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
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pkt_size = VID_PKT_SIZE(bt->width);
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dsi_write(rk628, 0, DSI_VID_PKT_SIZE, pkt_size);
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vactive = bt->height;
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vs = bt->vsync;
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vfp = bt->vfrontporch;
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vbp = bt->vbackporch;
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hs = bt->hsync;
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hbp = bt->hbackporch;
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hline = bt->width;
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dev_info(dsi->rk628->dev, "h: %d %d %d %d, v:%d %d %d %d clock:%llu\n",
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bt->width, bt->hfrontporch, bt->hsync, bt->hbackporch,
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bt->height, bt->vfrontporch, bt->vsync, bt->vbackporch,
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bt->pixelclock);
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//hline_time = hline * lanebyteclk / dpipclk;
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hline_time = DIV_ROUND_CLOSEST_ULL(hline * lanebyteclk, dpipclk);
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dsi_write(rk628, 0, DSI_VID_HLINE_TIME,
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VID_HLINE_TIME(hline_time));
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//hs_time = hs * lanebyteclk / dpipclk;
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hs_time = DIV_ROUND_CLOSEST_ULL(hs * lanebyteclk, dpipclk);
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dsi_write(rk628, 0, DSI_VID_HSA_TIME, VID_HSA_TIME(hs_time));
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//hbp_time = hbp * lanebyteclk / dpipclk;
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hbp_time = DIV_ROUND_CLOSEST_ULL(hbp * lanebyteclk, dpipclk);
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dsi_write(rk628, 0, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
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dsi_write(rk628, 0, DSI_VID_VACTIVE_LINES, vactive);
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dsi_write(rk628, 0, DSI_VID_VSA_LINES, vs);
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dsi_write(rk628, 0, DSI_VID_VFP_LINES, vfp);
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dsi_write(rk628, 0, DSI_VID_VBP_LINES, vbp);
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dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
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}
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static void rk628_dsi_set_cmd_mode(struct rk628_dsi *dsi)
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{
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struct rk628 *rk628 = dsi->rk628;
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dsi_update_bits(rk628, 0, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
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dsi_write(rk628, 0, DSI_EDPI_CMD_SIZE,
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EDPI_ALLOWED_CMD_SIZE(dsi->timings.bt.width));
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dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
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}
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static void rk628_dsi_enable(struct rk628_dsi *dsi)
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{
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u32 val;
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struct rk628 *rk628 = dsi->rk628;
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dsi_write(rk628, 0, DSI_PWR_UP, RESET);
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val = DPI_COLOR_CODING(5);
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dsi_write(rk628, 0, DSI_DPI_COLOR_CODING, val);
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val = 0;
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/*
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* if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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* val |= VSYNC_ACTIVE_LOW;
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* if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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* val |= HSYNC_ACTIVE_LOW;
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*/
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dsi_write(rk628, 0, DSI_DPI_CFG_POL, val);
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dsi_write(rk628, 0, DSI_DPI_VCID, DPI_VID(0));
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dsi_write(rk628, 0, DSI_DPI_LP_CMD_TIM,
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OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
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dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
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PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL,
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PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL);
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if (dsi->vid_mode == VIDEO_MODE)
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rk628_dsi_set_vid_mode(dsi);
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else
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rk628_dsi_set_cmd_mode(dsi);
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dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
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}
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static u32 rk628_dsi_get_lane_rate(struct rk628_dsi *dsi)
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{
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u32 lane_rate;
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u32 max_lane_rate = 1500;
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u8 bpp, lanes;
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u64 pixelclock = dsi->timings.bt.pixelclock;
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bpp = 24;
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lanes = 4;
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pixelclock = div_u64(pixelclock, 1000 * 1000);
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lane_rate = pixelclock * bpp;
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lane_rate = div_u64(lane_rate, lanes);
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lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
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if (lane_rate > max_lane_rate)
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lane_rate = max_lane_rate;
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return lane_rate;
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}
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void rk628_mipi_dsi_power_on(struct rk628_dsi *dsi)
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{
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struct rk628 *rk628 = dsi->rk628;
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u32 rate = rk628_dsi_get_lane_rate(dsi);
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int bus_width;
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
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SW_OUTPUT_MODE(OUTPUT_MODE_DSI));
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rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN, 0);
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bus_width = rate << 8;
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bus_width |= COMBTXPHY_MODULEA_EN;
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rk628_txphy_set_bus_width(dsi->rk628, bus_width);
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rk628_txphy_set_mode(dsi->rk628, PHY_MODE_VIDEO_MIPI);
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dsi->lane_mbps = rk628_txphy_get_bus_width(dsi->rk628);
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dev_dbg(dsi->rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__,
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dsi->lane_mbps);
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rk628_dsi_pre_enable(dsi);
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rk628_dsi_enable(dsi);
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}
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EXPORT_SYMBOL(rk628_mipi_dsi_power_on);
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