// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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static DEFINE_SPINLOCK(mod1_lock);
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#define SUN4I_MOD1_ENABLE 31
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#define SUN4I_MOD1_MUX 16
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#define SUN4I_MOD1_MUX_WIDTH 2
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#define SUN4I_MOD1_MAX_PARENTS 4
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static void __init sun4i_mod1_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_mux *mux;
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struct clk_gate *gate;
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const char *parents[4];
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const char *clk_name = node->name;
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void __iomem *reg;
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int i;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto err_unmap;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_free_mux;
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of_property_read_string(node, "clock-output-names", &clk_name);
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i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
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gate->reg = reg;
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gate->bit_idx = SUN4I_MOD1_ENABLE;
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gate->lock = &mod1_lock;
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mux->reg = reg;
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mux->shift = SUN4I_MOD1_MUX;
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mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
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mux->lock = &mod1_lock;
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clk = clk_register_composite(NULL, clk_name, parents, i,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
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if (IS_ERR(clk))
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goto err_free_gate;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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err_free_gate:
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kfree(gate);
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err_free_mux:
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kfree(mux);
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err_unmap:
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iounmap(reg);
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}
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CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
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sun4i_mod1_clk_setup);
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