/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/assembler.h>
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#include <asm/fpsimdmacros.h>
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#include <asm/kvm.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmu.h>
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#include <asm/kvm_ptrauth.h>
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.text
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/*
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* u64 __guest_enter(struct kvm_vcpu *vcpu);
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*/
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SYM_FUNC_START(__guest_enter)
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// x0: vcpu
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// x1-x17: clobbered by macros
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// x29: guest context
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adr_this_cpu x1, kvm_hyp_ctxt, x2
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// Store the hyp regs
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save_callee_saved_regs x1
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// Save hyp's sp_el0
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save_sp_el0 x1, x2
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// Now the hyp state is stored if we have a pending RAS SError it must
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// affect the host or hyp. If any asynchronous exception is pending we
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// defer the guest entry. The DSB isn't necessary before v8.2 as any
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// SError would be fatal.
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alternative_if ARM64_HAS_RAS_EXTN
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dsb nshst
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isb
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alternative_else_nop_endif
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mrs x1, isr_el1
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cbz x1, 1f
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mov x0, #ARM_EXCEPTION_IRQ
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ret
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1:
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set_loaded_vcpu x0, x1, x2
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add x29, x0, #VCPU_CONTEXT
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// Macro ptrauth_switch_to_guest format:
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// ptrauth_switch_to_guest(guest cxt, tmp1, tmp2, tmp3)
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// The below macro to restore guest keys is not implemented in C code
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// as it may cause Pointer Authentication key signing mismatch errors
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// when this feature is enabled for kernel code.
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ptrauth_switch_to_guest x29, x0, x1, x2
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// Restore the guest's sp_el0
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restore_sp_el0 x29, x0
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// Restore guest regs x0-x17
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ldp x0, x1, [x29, #CPU_XREG_OFFSET(0)]
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ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)]
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ldp x4, x5, [x29, #CPU_XREG_OFFSET(4)]
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ldp x6, x7, [x29, #CPU_XREG_OFFSET(6)]
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ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)]
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ldp x10, x11, [x29, #CPU_XREG_OFFSET(10)]
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ldp x12, x13, [x29, #CPU_XREG_OFFSET(12)]
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ldp x14, x15, [x29, #CPU_XREG_OFFSET(14)]
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ldp x16, x17, [x29, #CPU_XREG_OFFSET(16)]
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// Restore guest regs x18-x29, lr
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restore_callee_saved_regs x29
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// Do not touch any register after this!
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eret
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sb
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SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL)
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// x2-x29,lr: vcpu regs
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// vcpu x0-x1 on the stack
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// If the hyp context is loaded, go straight to hyp_panic
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get_loaded_vcpu x0, x1
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cbnz x0, 1f
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b hyp_panic
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1:
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// The hyp context is saved so make sure it is restored to allow
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// hyp_panic to run at hyp and, subsequently, panic to run in the host.
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// This makes use of __guest_exit to avoid duplication but sets the
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// return address to tail call into hyp_panic. As a side effect, the
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// current state is saved to the guest context but it will only be
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// accurate if the guest had been completely restored.
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adr_this_cpu x0, kvm_hyp_ctxt, x1
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adr_l x1, hyp_panic
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str x1, [x0, #CPU_XREG_OFFSET(30)]
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get_vcpu_ptr x1, x0
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SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL)
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// x0: return code
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// x1: vcpu
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// x2-x29,lr: vcpu regs
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// vcpu x0-x1 on the stack
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add x1, x1, #VCPU_CONTEXT
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ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
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// Store the guest regs x2 and x3
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stp x2, x3, [x1, #CPU_XREG_OFFSET(2)]
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// Retrieve the guest regs x0-x1 from the stack
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ldp x2, x3, [sp], #16 // x0, x1
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// Store the guest regs x0-x1 and x4-x17
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stp x2, x3, [x1, #CPU_XREG_OFFSET(0)]
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stp x4, x5, [x1, #CPU_XREG_OFFSET(4)]
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stp x6, x7, [x1, #CPU_XREG_OFFSET(6)]
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stp x8, x9, [x1, #CPU_XREG_OFFSET(8)]
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stp x10, x11, [x1, #CPU_XREG_OFFSET(10)]
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stp x12, x13, [x1, #CPU_XREG_OFFSET(12)]
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stp x14, x15, [x1, #CPU_XREG_OFFSET(14)]
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stp x16, x17, [x1, #CPU_XREG_OFFSET(16)]
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// Store the guest regs x18-x29, lr
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save_callee_saved_regs x1
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// Store the guest's sp_el0
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save_sp_el0 x1, x2
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adr_this_cpu x2, kvm_hyp_ctxt, x3
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// Macro ptrauth_switch_to_hyp format:
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// ptrauth_switch_to_hyp(guest cxt, host cxt, tmp1, tmp2, tmp3)
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// The below macro to save/restore keys is not implemented in C code
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// as it may cause Pointer Authentication key signing mismatch errors
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// when this feature is enabled for kernel code.
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ptrauth_switch_to_hyp x1, x2, x3, x4, x5
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// Restore hyp's sp_el0
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restore_sp_el0 x2, x3
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// Now restore the hyp regs
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restore_callee_saved_regs x2
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set_loaded_vcpu xzr, x2, x3
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alternative_if ARM64_HAS_RAS_EXTN
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// If we have the RAS extensions we can consume a pending error
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// without an unmask-SError and isb. The ESB-instruction consumed any
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// pending guest error when we took the exception from the guest.
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mrs_s x2, SYS_DISR_EL1
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str x2, [x1, #(VCPU_FAULT_DISR - VCPU_CONTEXT)]
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cbz x2, 1f
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msr_s SYS_DISR_EL1, xzr
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orr x0, x0, #(1<<ARM_EXIT_WITH_SERROR_BIT)
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1: ret
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alternative_else
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dsb sy // Synchronize against in-flight ld/st
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isb // Prevent an early read of side-effect free ISR
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mrs x2, isr_el1
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tbnz x2, #8, 2f // ISR_EL1.A
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ret
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nop
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2:
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alternative_endif
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// We know we have a pending asynchronous abort, now is the
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// time to flush it out. From your VAXorcist book, page 666:
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// "Threaten me not, oh Evil one! For I speak with
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// the power of DEC, and I command thee to show thyself!"
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mrs x2, elr_el2
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mrs x3, esr_el2
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mrs x4, spsr_el2
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mov x5, x0
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msr daifclr, #4 // Unmask aborts
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// This is our single instruction exception window. A pending
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// SError is guaranteed to occur at the earliest when we unmask
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// it, and at the latest just after the ISB.
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abort_guest_exit_start:
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isb
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abort_guest_exit_end:
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msr daifset, #4 // Mask aborts
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ret
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_kvm_extable abort_guest_exit_start, 9997f
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_kvm_extable abort_guest_exit_end, 9997f
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9997:
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msr daifset, #4 // Mask aborts
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mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
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// restore the EL1 exception context so that we can report some
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// information. Merge the exception code with the SError pending bit.
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msr elr_el2, x2
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msr esr_el2, x3
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msr spsr_el2, x4
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orr x0, x0, x5
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1: ret
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SYM_FUNC_END(__guest_enter)
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