// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2011 Samsung Electronics Co.Ltd
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// Author: Joonyoung Shim <jy0922.shim@samsung.com>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include "map.h"
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#include "cpu.h"
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#include "usb-phy.h"
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#include "regs-sys-s3c64xx.h"
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#include "regs-usb-hsotg-phy-s3c64xx.h"
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enum samsung_usb_phy_type {
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USB_PHY_TYPE_DEVICE,
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USB_PHY_TYPE_HOST,
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};
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static int s3c_usb_otgphy_init(struct platform_device *pdev)
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{
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struct clk *xusbxti;
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u32 phyclk;
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writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
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/* set clock frequency for PLL */
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phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
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xusbxti = clk_get(&pdev->dev, "xusbxti");
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if (!IS_ERR(xusbxti)) {
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switch (clk_get_rate(xusbxti)) {
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case 12 * MHZ:
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phyclk |= S3C_PHYCLK_CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= S3C_PHYCLK_CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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}
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clk_put(xusbxti);
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}
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/* TODO: select external clock/oscillator */
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writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
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/* set to normal OTG PHY */
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writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
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mdelay(1);
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/* reset OTG PHY and Link */
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writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
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S3C_RSTCON);
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udelay(20); /* at-least 10uS */
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writel(0, S3C_RSTCON);
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return 0;
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}
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static int s3c_usb_otgphy_exit(struct platform_device *pdev)
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{
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writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
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S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
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writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
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return 0;
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}
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int s3c_usb_phy_init(struct platform_device *pdev, int type)
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{
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if (type == USB_PHY_TYPE_DEVICE)
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return s3c_usb_otgphy_init(pdev);
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return -EINVAL;
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}
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int s3c_usb_phy_exit(struct platform_device *pdev, int type)
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{
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if (type == USB_PHY_TYPE_DEVICE)
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return s3c_usb_otgphy_exit(pdev);
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return -EINVAL;
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}
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