/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* MMP2 Power Management Routines
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*
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* (C) Copyright 2010 Marvell International Ltd.
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* All Rights Reserved
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*/
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#ifndef __MMP2_PM_H__
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#define __MMP2_PM_H__
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#include "addr-map.h"
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#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
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#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
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#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
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#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
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#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
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#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
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#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
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#define MPMU_SCCR MPMU_REG(0x038)
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#define MPMU_PCR_PJ MPMU_REG(0x1000)
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#define MPMU_PCR_PJ_AXISD (1 << 31)
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#define MPMU_PCR_PJ_SLPEN (1 << 29)
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#define MPMU_PCR_PJ_SPSD (1 << 28)
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#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
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#define MPMU_PCR_PJ_APBSD (1 << 26)
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#define MPMU_PCR_PJ_INTCLR (1 << 24)
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#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
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#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
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#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
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#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
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#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
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#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
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#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
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#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
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#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
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#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
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#define MPMU_CGR_PJ MPMU_REG(0x1024)
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#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
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#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
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#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
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enum {
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POWER_MODE_ACTIVE = 0,
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POWER_MODE_CORE_INTIDLE,
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POWER_MODE_CORE_EXTIDLE,
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POWER_MODE_APPS_IDLE,
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POWER_MODE_APPS_SLEEP,
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POWER_MODE_CHIP_SLEEP,
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POWER_MODE_SYS_SLEEP,
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};
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extern void mmp2_pm_enter_lowpower_mode(int state);
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extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
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#endif
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