/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "vepu541_common"
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#include <string.h>
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#include "mpp_mem.h"
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#include "mpp_debug.h"
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#include "mpp_common.h"
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#include "vepu541_common.h"
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static const RK_S32 zeros[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
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static VepuFmtCfg vepu541_yuv_cfg[MPP_FMT_YUV_BUTT] = {
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{ /* MPP_FMT_YUV420SP */
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.format = VEPU541_FMT_YUV420SP,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV420SP_10BIT */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422SP */
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.format = VEPU541_FMT_YUV422SP,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422SP_10BIT */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV420P */
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.format = VEPU541_FMT_YUV420P,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV420SP_VU */
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.format = VEPU541_FMT_YUV420SP,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422P */
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.format = VEPU541_FMT_YUV422P,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422SP_VU */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422_YUYV */
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.format = VEPU541_FMT_YUYV422,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422_YVYU */
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.format = VEPU541_FMT_YUYV422,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422_UYVY */
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.format = VEPU541_FMT_UYVY422,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV422_VYUY */
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.format = VEPU541_FMT_UYVY422,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV400 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV440SP */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV411SP */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV444SP */
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.format = VEPU580_FMT_YUV444SP,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_YUV444P */
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.format = VEPU580_FMT_YUV444P,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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};
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static VepuFmtCfg vepu541_rgb_cfg[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
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{ /* MPP_FMT_RGB565 */
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.format = VEPU541_FMT_BGR565,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 1,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGR565 */
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.format = VEPU541_FMT_BGR565,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 1,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_RGB555 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGR555 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_RGB444 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGR444 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_RGB888 */
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.format = VEPU541_FMT_BGR888,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGR888 */
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.format = VEPU541_FMT_BGR888,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_RGB101010 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGR101010 */
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.format = VEPU541_FMT_NONE,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_ARGB8888 */
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.format = VEPU541_FMT_BGRA8888,
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.alpha_swap = 1,
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.rbuv_swap = 1,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_ABGR8888 */
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.format = VEPU541_FMT_BGRA8888,
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.alpha_swap = 1,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_BGRA8888 */
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.format = VEPU541_FMT_BGRA8888,
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.alpha_swap = 0,
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.rbuv_swap = 0,
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.src_range = 0,
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.src_endian = 0,
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.weight = zeros,
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.offset = zeros,
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},
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{ /* MPP_FMT_RGBA8888 */
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.format = VEPU541_FMT_BGRA8888,
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.alpha_swap = 0,
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.rbuv_swap = 1,
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.src_endian = 0,
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.src_range = 0,
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.weight = zeros,
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.offset = zeros,
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},
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};
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MPP_RET vepu541_set_fmt(VepuFmtCfg *cfg, MppFrameFormat format)
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{
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VepuFmtCfg *fmt = NULL;
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MPP_RET ret = MPP_OK;
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format &= MPP_FRAME_FMT_MASK;
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if (MPP_FRAME_FMT_IS_YUV(format)) {
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fmt = &vepu541_yuv_cfg[format - MPP_FRAME_FMT_YUV];
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} else if (MPP_FRAME_FMT_IS_RGB(format)) {
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fmt = &vepu541_rgb_cfg[format - MPP_FRAME_FMT_RGB];
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} else {
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memset(cfg, 0, sizeof(*cfg));
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cfg->format = VEPU541_FMT_NONE;
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}
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if (fmt && fmt->format != VEPU541_FMT_NONE) {
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memcpy(cfg, fmt, sizeof(*cfg));
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} else {
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mpp_err_f("unsupport frame format %x\n", format);
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cfg->format = VEPU541_FMT_NONE;
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ret = MPP_NOK;
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}
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return ret;
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}
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RK_S32 vepu541_get_roi_buf_size(RK_S32 w, RK_S32 h)
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{
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RK_S32 stride_h = MPP_ALIGN(w, 64) / 16;
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RK_S32 stride_v = MPP_ALIGN(h, 64) / 16;
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RK_S32 buf_size = stride_h * stride_v * sizeof(Vepu541RoiCfg);
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/* extra 32 byte for hardware access padding */
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return buf_size + 32;
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}
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MPP_RET vepu541_set_roi(void *buf, MppEncROICfg *roi, RK_S32 w, RK_S32 h)
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{
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MppEncROIRegion *region = roi->regions;
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Vepu541RoiCfg *ptr = (Vepu541RoiCfg *)buf;
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RK_S32 mb_w = MPP_ALIGN(w, 16) / 16;
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RK_S32 mb_h = MPP_ALIGN(h, 16) / 16;
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RK_S32 stride_h = MPP_ALIGN(mb_w, 4);
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RK_S32 stride_v = MPP_ALIGN(mb_h, 4);
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Vepu541RoiCfg cfg;
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MPP_RET ret = MPP_NOK;
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RK_S32 i;
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if (NULL == buf || NULL == roi) {
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mpp_err_f("invalid buf %p roi %p\n", buf, roi);
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goto DONE;
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}
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cfg.force_intra = 0;
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cfg.reserved = 0;
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cfg.qp_area_idx = 0;
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cfg.qp_area_en = 1;
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cfg.qp_adj = 0;
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cfg.qp_adj_mode = 0;
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/* step 1. reset all the config */
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for (i = 0; i < stride_h * stride_v; i++, ptr++)
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memcpy(ptr, &cfg, sizeof(cfg));
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if (w <= 0 || h <= 0) {
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mpp_err_f("invalid size [%d:%d]\n", w, h);
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goto DONE;
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}
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if (roi->number > VEPU541_MAX_ROI_NUM) {
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mpp_err_f("invalid region number %d\n", roi->number);
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goto DONE;
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}
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/* check region config */
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ret = MPP_OK;
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for (i = 0; i < (RK_S32)roi->number; i++, region++) {
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if (region->x + region->w > w || region->y + region->h > h)
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ret = MPP_NOK;
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if (region->intra > 1 || region->qp_area_idx >= VEPU541_MAX_ROI_NUM ||
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region->area_map_en > 1 || region->abs_qp_en > 1)
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ret = MPP_NOK;
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if ((region->abs_qp_en && region->quality > 51) ||
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(!region->abs_qp_en && (region->quality > 51 || region->quality < -51)))
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ret = MPP_NOK;
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if (ret) {
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mpp_err_f("region %d invalid param:\n", i);
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mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
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region->x, region->y, region->w, region->h, w, h);
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mpp_err_f("force intra %d qp area index %d\n",
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region->intra, region->qp_area_idx);
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mpp_err_f("abs qp mode %d value %d\n",
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region->abs_qp_en, region->quality);
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goto DONE;
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}
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}
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region = roi->regions;
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/* step 2. setup region for top to bottom */
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for (i = 0; i < (RK_S32)roi->number; i++, region++) {
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RK_S32 roi_width = (region->w + 15) / 16;
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RK_S32 roi_height = (region->h + 15) / 16;
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RK_S32 pos_x_init = (region->x + 15) / 16;
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RK_S32 pos_y_init = (region->y + 15) / 16;
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RK_S32 pos_x_end = pos_x_init + roi_width;
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RK_S32 pos_y_end = pos_y_init + roi_height;
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RK_S32 x, y;
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mpp_assert(pos_x_init >= 0 && pos_x_init < mb_w);
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mpp_assert(pos_x_end >= 0 && pos_x_end <= mb_w);
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mpp_assert(pos_y_init >= 0 && pos_y_init < mb_h);
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mpp_assert(pos_y_end >= 0 && pos_y_end <= mb_h);
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cfg.force_intra = region->intra;
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cfg.reserved = 0;
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cfg.qp_area_idx = region->qp_area_idx;
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// NOTE: When roi is enabled the qp_area_en should be one.
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cfg.qp_area_en = 1; // region->area_map_en;
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cfg.qp_adj = region->quality;
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cfg.qp_adj_mode = region->abs_qp_en;
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ptr = (Vepu541RoiCfg *)buf;
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ptr += pos_y_init * stride_h + pos_x_init;
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for (y = 0; y < roi_height; y++) {
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Vepu541RoiCfg *dst = ptr;
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for (x = 0; x < roi_width; x++, dst++)
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memcpy(dst, &cfg, sizeof(cfg));
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ptr += stride_h;
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}
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}
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DONE:
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return ret;
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}
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/*
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* Invert color threshold is for the absolute difference between background
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* and foregroud color.
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* If background color and foregroud color are close enough then trigger the
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* invert color process.
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*/
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#define ENC_DEFAULT_OSD_INV_THR 15
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#define VEPU541_OSD_ADDR_IDX_BASE 124
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#define VEPU580_OSD_ADDR_IDX_BASE 3092
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#define VEPU541_OSD_CFG_OFFSET 0x01C0
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#define VEPU541_OSD_PLT_OFFSET 0x0400
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typedef enum Vepu541OsdPltType_e {
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VEPU541_OSD_PLT_TYPE_USERDEF = 0,
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VEPU541_OSD_PLT_TYPE_DEFAULT = 1,
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} Vepu541OsdPltType;
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typedef struct Vepu541OsdReg_t {
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/*
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* OSD_CFG
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* Address offset: 0x01C0 Access type: read and write
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* OSD configuration
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*/
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struct {
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/* OSD region enable, each bit controls corresponding OSD region. */
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RK_U32 osd_e : 8;
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/* OSD inverse color enable, each bit controls corresponding region. */
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RK_U32 osd_inv_e : 8;
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/*
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* OSD palette clock selection.
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* 1'h0: Configure bus clock domain.
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* 1'h1: Core clock domain.
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*/
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RK_U32 osd_plt_cks : 1;
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/*
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* OSD palette type.
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* 1'h1: Default type.
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* 1'h0: User defined type.
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*/
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RK_U32 osd_plt_typ : 1;
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RK_U32 reserved : 14;
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} reg112;
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/*
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* OSD_INV
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* Address offset: 0x01C4 Access type: read and write
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* OSD color inverse configuration
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*/
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struct {
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/* Color inverse theshold for OSD region0. */
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RK_U32 osd_ithd_r0 : 4;
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/* Color inverse theshold for OSD region1. */
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RK_U32 osd_ithd_r1 : 4;
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/* Color inverse theshold for OSD region2. */
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RK_U32 osd_ithd_r2 : 4;
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/* Color inverse theshold for OSD region3. */
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RK_U32 osd_ithd_r3 : 4;
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/* Color inverse theshold for OSD region4. */
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RK_U32 osd_ithd_r4 : 4;
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/* Color inverse theshold for OSD region5. */
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RK_U32 osd_ithd_r5 : 4;
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/* Color inverse theshold for OSD region6. */
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RK_U32 osd_ithd_r6 : 4;
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/* Color inverse theshold for OSD region7. */
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RK_U32 osd_ithd_r7 : 4;
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} reg113;
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RK_U32 reg114;
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RK_U32 reg115;
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/*
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* OSD_POS reg116_123
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* Address offset: 0x01D0~0x01EC Access type: read and write
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* OSD region position
|
*/
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Vepu541OsdPos osd_pos[8];
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/*
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* ADR_OSD reg124_131
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* Address offset: 0x01F0~0x20C Access type: read and write
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* Base address for OSD region, 16B aligned
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*/
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RK_U32 osd_addr[8];
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} Vepu541OsdReg;
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#define SET_OSD_INV_THR(index, reg, region)\
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if(region[index].inverse) \
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reg.osd_ithd_r##index = ENC_DEFAULT_OSD_INV_THR;
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static MPP_RET copy2osd2(MppEncOSDData2* dst, MppEncOSDData *src1, MppEncOSDData2 *src2)
|
{
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MPP_RET ret = MPP_OK;
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RK_U32 i = 0;
|
|
if (src1) {
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dst->num_region = src1->num_region;
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for (i = 0; i < src1->num_region; i++) {
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dst->region[i].enable = src1->region[i].enable;
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dst->region[i].inverse = src1->region[i].inverse;
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dst->region[i].start_mb_x = src1->region[i].start_mb_x;
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dst->region[i].start_mb_y = src1->region[i].start_mb_y;
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dst->region[i].num_mb_x = src1->region[i].num_mb_x;
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dst->region[i].num_mb_y = src1->region[i].num_mb_y;
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dst->region[i].buf_offset = src1->region[i].buf_offset;
|
dst->region[i].buf = src1->buf;
|
}
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ret = MPP_OK;
|
} else if (src2) {
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memcpy(dst, src2, sizeof(MppEncOSDData2));
|
ret = MPP_OK;
|
} else {
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ret = MPP_NOK;
|
}
|
return ret;
|
}
|
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MPP_RET vepu541_set_osd(Vepu541OsdCfg *cfg)
|
{
|
Vepu541OsdReg *regs = (Vepu541OsdReg *)(cfg->reg_base + (size_t)VEPU541_OSD_CFG_OFFSET);
|
MppDev dev = cfg->dev;
|
MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
|
MppEncOSDData2 osd;
|
|
if (copy2osd2(&osd, cfg->osd_data, cfg->osd_data2))
|
return MPP_NOK;
|
|
if (osd.num_region == 0)
|
return MPP_OK;
|
|
if (osd.num_region > 8) {
|
mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
|
osd.num_region);
|
mpp_assert(osd.num_region <= 8);
|
return MPP_NOK;
|
}
|
|
if (plt_cfg->type == MPP_ENC_OSD_PLT_TYPE_USERDEF) {
|
MppDevRegWrCfg wr_cfg;
|
|
wr_cfg.reg = plt_cfg->plt;
|
wr_cfg.size = sizeof(MppEncOSDPlt);
|
wr_cfg.offset = VEPU541_REG_BASE_OSD_PLT;
|
|
mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
|
|
regs->reg112.osd_plt_cks = 1;
|
regs->reg112.osd_plt_typ = VEPU541_OSD_PLT_TYPE_USERDEF;
|
} else {
|
regs->reg112.osd_plt_cks = 0;
|
regs->reg112.osd_plt_typ = VEPU541_OSD_PLT_TYPE_DEFAULT;
|
}
|
|
regs->reg112.osd_e = 0;
|
regs->reg112.osd_inv_e = 0;
|
|
RK_U32 i = 0;
|
MppEncOSDRegion2 *region = osd.region;
|
MppEncOSDRegion2 *tmp = region;
|
RK_U32 num = osd.num_region;
|
|
for (i = 0; i < num; i++, tmp++) {
|
regs->reg112.osd_e |= tmp->enable << i;
|
regs->reg112.osd_inv_e |= tmp->inverse << i;
|
|
if (tmp->enable && tmp->num_mb_x && tmp->num_mb_y) {
|
Vepu541OsdPos *pos = ®s->osd_pos[i];
|
size_t blk_len = tmp->num_mb_x * tmp->num_mb_y * 256;
|
RK_S32 fd = 0;
|
RK_U32 buf_size = 0;
|
|
pos->osd_lt_x = tmp->start_mb_x;
|
pos->osd_lt_y = tmp->start_mb_y;
|
pos->osd_rb_x = tmp->start_mb_x + tmp->num_mb_x - 1;
|
pos->osd_rb_y = tmp->start_mb_y + tmp->num_mb_y - 1;
|
|
buf_size = mpp_buffer_get_size(tmp->buf);
|
fd = mpp_buffer_get_fd(tmp->buf);
|
if (fd < 0) {
|
mpp_err_f("invalid osd buffer fd %d\n", fd);
|
return MPP_NOK;
|
}
|
regs->osd_addr[i] = fd;
|
|
if (tmp->buf_offset) {
|
MppDevRegOffsetCfg trans_cfg;
|
|
trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + i;
|
trans_cfg.offset = tmp->buf_offset;
|
mpp_dev_ioctl(cfg->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
|
}
|
|
/* There should be enough buffer and offset should be 16B aligned */
|
if (buf_size < tmp->buf_offset + blk_len ||
|
(tmp->buf_offset & 0xf)) {
|
mpp_err_f("invalid osd cfg: %d x:y:w:h:off %d:%d:%d:%d:%x\n",
|
i, tmp->start_mb_x, tmp->start_mb_y,
|
tmp->num_mb_x, tmp->num_mb_y, tmp->buf_offset);
|
}
|
}
|
}
|
|
SET_OSD_INV_THR(0, regs->reg113, region);
|
SET_OSD_INV_THR(1, regs->reg113, region);
|
SET_OSD_INV_THR(2, regs->reg113, region);
|
SET_OSD_INV_THR(3, regs->reg113, region);
|
SET_OSD_INV_THR(4, regs->reg113, region);
|
SET_OSD_INV_THR(5, regs->reg113, region);
|
SET_OSD_INV_THR(6, regs->reg113, region);
|
SET_OSD_INV_THR(7, regs->reg113, region);
|
|
return MPP_OK;
|
}
|
|
#define VEPU540_OSD_CFG_OFFSET 0x0178
|
|
typedef struct Vepu540OsdReg_t {
|
/*
|
* OSD_INV_CFG
|
* Address offset: 0x0178 Access type: read and write
|
* OSD color inverse configuration
|
*/
|
struct {
|
/*
|
* OSD color inverse enable of chroma component,
|
* each bit controls corresponding region.
|
*/
|
RK_U32 osd_ch_inv_en : 8;
|
/*
|
* OSD color inverse expression type
|
* each bit controls corresponding region.
|
* 1'h0: AND;
|
* 1'h1: OR
|
*/
|
RK_U32 osd_itype : 8;
|
/*
|
* OSD color inverse expression switch for luma component
|
* each bit controls corresponding region.
|
* 1'h0: Expression need to determine the condition;
|
* 1'h1: Expression don't need to determine the condition;
|
*/
|
RK_U32 osd_lu_inv_msk : 8;
|
/*
|
* OSD color inverse expression switch for chroma component
|
* each bit controls corresponding region.
|
* 1'h0: Expression need to determine the condition;
|
* 1'h1: Expression don't need to determine the condition;
|
*/
|
RK_U32 osd_ch_inv_msk : 8;
|
} reg094;
|
|
/* reg gap 095~111 */
|
RK_U32 reg_095_111[17];
|
|
/*
|
* OSD_CFG
|
* Address offset: 0x01C0 Access type: read and write
|
* OSD configuration
|
*/
|
struct {
|
/* OSD region enable, each bit controls corresponding OSD region. */
|
RK_U32 osd_e : 8;
|
/* OSD inverse color enable, each bit controls corresponding region. */
|
RK_U32 osd_lu_inv_en : 8;
|
/*
|
* OSD palette clock selection.
|
* 1'h0: Configure bus clock domain.
|
* 1'h1: Core clock domain.
|
*/
|
RK_U32 osd_plt_cks : 1;
|
/*
|
* OSD palette type.
|
* 1'h1: Default type.
|
* 1'h0: User defined type.
|
*/
|
RK_U32 osd_plt_typ : 1;
|
RK_U32 reserved : 14;
|
} reg112;
|
|
/*
|
* OSD_INV
|
* Address offset: 0x01C4 Access type: read and write
|
* OSD color inverse configuration
|
*/
|
struct {
|
/* Color inverse theshold for OSD region0. */
|
RK_U32 osd_ithd_r0 : 4;
|
/* Color inverse theshold for OSD region1. */
|
RK_U32 osd_ithd_r1 : 4;
|
/* Color inverse theshold for OSD region2. */
|
RK_U32 osd_ithd_r2 : 4;
|
/* Color inverse theshold for OSD region3. */
|
RK_U32 osd_ithd_r3 : 4;
|
/* Color inverse theshold for OSD region4. */
|
RK_U32 osd_ithd_r4 : 4;
|
/* Color inverse theshold for OSD region5. */
|
RK_U32 osd_ithd_r5 : 4;
|
/* Color inverse theshold for OSD region6. */
|
RK_U32 osd_ithd_r6 : 4;
|
/* Color inverse theshold for OSD region7. */
|
RK_U32 osd_ithd_r7 : 4;
|
} reg113;
|
|
RK_U32 reg114;
|
RK_U32 reg115;
|
|
/*
|
* OSD_POS reg116_123
|
* Address offset: 0x01D0~0x01EC Access type: read and write
|
* OSD region position
|
*/
|
Vepu541OsdPos osd_pos[8];
|
|
/*
|
* ADR_OSD reg124_131
|
* Address offset: 0x01F0~0x20C Access type: read and write
|
* Base address for OSD region, 16B aligned
|
*/
|
RK_U32 osd_addr[8];
|
} Vepu540OsdReg;
|
|
MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
|
{
|
Vepu540OsdReg *regs = (Vepu540OsdReg *)(cfg->reg_base + (size_t)VEPU540_OSD_CFG_OFFSET);
|
MppDev dev = cfg->dev;
|
MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
|
MppEncOSDData2 osd;
|
|
if (copy2osd2(&osd, cfg->osd_data, cfg->osd_data2))
|
return MPP_NOK;
|
|
if (osd.num_region == 0)
|
return MPP_OK;
|
|
if (osd.num_region > 8) {
|
mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
|
osd.num_region);
|
mpp_assert(osd.num_region <= 8);
|
return MPP_NOK;
|
}
|
|
if (plt_cfg->type == MPP_ENC_OSD_PLT_TYPE_USERDEF) {
|
MppDevRegWrCfg wr_cfg;
|
|
wr_cfg.reg = plt_cfg->plt;
|
wr_cfg.size = sizeof(MppEncOSDPlt);
|
wr_cfg.offset = VEPU541_REG_BASE_OSD_PLT;
|
mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
|
|
regs->reg112.osd_plt_cks = 1;
|
regs->reg112.osd_plt_typ = VEPU541_OSD_PLT_TYPE_USERDEF;
|
} else {
|
regs->reg112.osd_plt_cks = 0;
|
regs->reg112.osd_plt_typ = VEPU541_OSD_PLT_TYPE_DEFAULT;
|
}
|
|
regs->reg112.osd_e = 0;
|
regs->reg112.osd_lu_inv_en = 0;
|
regs->reg094.osd_ch_inv_en = 0;
|
regs->reg094.osd_lu_inv_msk = 0;
|
|
RK_U32 num = osd.num_region;
|
RK_U32 k = 0;
|
MppEncOSDRegion2 *region = osd.region;
|
MppEncOSDRegion2 *tmp = region;
|
|
for (k = 0; k < num; k++, tmp++) {
|
regs->reg112.osd_e |= tmp->enable << k;
|
regs->reg112.osd_lu_inv_en |= (tmp->inverse) ? (1 << k) : 0;
|
regs->reg094.osd_ch_inv_en |= (tmp->inverse) ? (1 << k) : 0;
|
|
if (tmp->enable && tmp->num_mb_x && tmp->num_mb_y) {
|
Vepu541OsdPos *pos = ®s->osd_pos[k];
|
size_t blk_len = tmp->num_mb_x * tmp->num_mb_y * 256;
|
RK_S32 fd = -1;
|
size_t buf_size = 0;
|
|
pos->osd_lt_x = tmp->start_mb_x;
|
pos->osd_lt_y = tmp->start_mb_y;
|
pos->osd_rb_x = tmp->start_mb_x + tmp->num_mb_x - 1;
|
pos->osd_rb_y = tmp->start_mb_y + tmp->num_mb_y - 1;
|
|
buf_size = mpp_buffer_get_size(tmp->buf);
|
fd = mpp_buffer_get_fd(tmp->buf);
|
if (fd < 0) {
|
mpp_err_f("invalid osd buffer fd %d\n", fd);
|
return MPP_NOK;
|
}
|
regs->osd_addr[k] = fd;
|
|
if (tmp->buf_offset) {
|
MppDevRegOffsetCfg trans_cfg;
|
|
trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + k;
|
trans_cfg.offset = tmp->buf_offset;
|
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
|
}
|
|
/* There should be enough buffer and offset should be 16B aligned */
|
if (buf_size < tmp->buf_offset + blk_len ||
|
(tmp->buf_offset & 0xf)) {
|
mpp_err_f("invalid osd cfg: %d x:y:w:h:off %d:%d:%d:%d:%x size %x\n",
|
k, tmp->start_mb_x, tmp->start_mb_y,
|
tmp->num_mb_x, tmp->num_mb_y, tmp->buf_offset, buf_size);
|
}
|
}
|
}
|
|
SET_OSD_INV_THR(0, regs->reg113, region);
|
SET_OSD_INV_THR(1, regs->reg113, region);
|
SET_OSD_INV_THR(2, regs->reg113, region);
|
SET_OSD_INV_THR(3, regs->reg113, region);
|
SET_OSD_INV_THR(4, regs->reg113, region);
|
SET_OSD_INV_THR(5, regs->reg113, region);
|
SET_OSD_INV_THR(6, regs->reg113, region);
|
SET_OSD_INV_THR(7, regs->reg113, region);
|
|
return MPP_OK;
|
}
|
|
typedef struct Vepu580OsdReg_t {
|
/*
|
* OSD_INV_CFG
|
* Address offset: 0x00003000 Access type: read and write
|
* OSD color inverse configuration
|
*/
|
struct {
|
/*
|
* OSD color inverse enable of luma component,
|
* each bit controls corresponding region.
|
*/
|
RK_U32 osd_lu_inv_en : 8;
|
|
/* OSD color inverse enable of chroma component,
|
* each bit controls corresponding region.
|
*/
|
RK_U32 osd_ch_inv_en : 8;
|
/*
|
* OSD color inverse expression switch for luma component
|
* each bit controls corresponding region.
|
* 1'h0: Expression need to determine the condition;
|
* 1'h1: Expression don't need to determine the condition;
|
*/
|
RK_U32 osd_lu_inv_msk : 8;
|
/*
|
* OSD color inverse expression switch for chroma component
|
* each bit controls corresponding region.
|
* 1'h0: Expression need to determine the condition;
|
* 1'h1: Expression don't need to determine the condition;
|
*/
|
RK_U32 osd_ch_inv_msk : 8;
|
} reg3072;
|
|
/*
|
* OSD_INV
|
* Address offset: 0x3004 Access type: read and write
|
* OSD color inverse configuration
|
*/
|
struct {
|
/* Color inverse theshold for OSD region0. */
|
RK_U32 osd_ithd_r0 : 4;
|
/* Color inverse theshold for OSD region1. */
|
RK_U32 osd_ithd_r1 : 4;
|
/* Color inverse theshold for OSD region2. */
|
RK_U32 osd_ithd_r2 : 4;
|
/* Color inverse theshold for OSD region3. */
|
RK_U32 osd_ithd_r3 : 4;
|
/* Color inverse theshold for OSD region4. */
|
RK_U32 osd_ithd_r4 : 4;
|
/* Color inverse theshold for OSD region5. */
|
RK_U32 osd_ithd_r5 : 4;
|
/* Color inverse theshold for OSD region6. */
|
RK_U32 osd_ithd_r6 : 4;
|
/* Color inverse theshold for OSD region7. */
|
RK_U32 osd_ithd_r7 : 4;
|
} reg3073;
|
|
/*
|
* OSD_CFG
|
* Address offset: 0x3008 Access type: read and write
|
* OSD configuration
|
*/
|
struct {
|
/* OSD region enable, each bit controls corresponding OSD region. */
|
RK_U32 osd_e : 8;
|
/*
|
* OSD color inverse expression type
|
* each bit controls corresponding region.
|
* 1'h0: AND;
|
* 1'h1: OR
|
*/
|
RK_U32 osd_itype : 8;
|
/*
|
* OSD palette clock selection.
|
* 1'h0: Configure bus clock domain.
|
* 1'h1: Core clock domain.
|
*/
|
RK_U32 osd_plt_cks : 1;
|
/*
|
* OSD palette type.
|
* 1'h1: Default type.
|
* 1'h0: User defined type.
|
*/
|
RK_U32 osd_plt_typ : 1;
|
RK_U32 reserved : 14;
|
} reg3074;
|
|
RK_U32 reserved_3075;
|
/*
|
* OSD_POS reg3076_reg3091
|
* Address offset: 0x3010~0x304c Access type: read and write
|
* OSD region position
|
*/
|
Vepu580OsdPos osd_pos[8];
|
|
/*
|
* ADR_OSD reg3092_reg3099
|
* Address offset: 0x00003050~reg306c Access type: read and write
|
* Base address for OSD region, 16B aligned
|
*/
|
RK_U32 osd_addr[8];
|
|
RK_U32 reserved3100_3103[4];
|
Vepu541OsdPltColor plt_data[256];
|
} Vepu580OsdReg;
|
|
MPP_RET vepu580_set_osd(Vepu541OsdCfg *cfg)
|
{
|
Vepu580OsdReg *regs = (Vepu580OsdReg *)cfg->reg_base;
|
MppDev dev = cfg->dev;
|
MppDevRegOffCfgs *reg_cfg = cfg->reg_cfg;
|
MppEncOSDPltCfg *plt_cfg = cfg->plt_cfg;
|
MppEncOSDData2 osd;
|
|
if (copy2osd2(&osd, cfg->osd_data, cfg->osd_data2))
|
return MPP_NOK;
|
|
if (osd.num_region == 0)
|
return MPP_OK;
|
|
if (osd.num_region > 8) {
|
mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
|
osd.num_region);
|
mpp_assert(osd.num_region <= 8);
|
return MPP_NOK;
|
}
|
|
if (plt_cfg->type == MPP_ENC_OSD_PLT_TYPE_USERDEF) {
|
memcpy(regs->plt_data, plt_cfg->plt, sizeof(MppEncOSDPlt));
|
regs->reg3074.osd_plt_cks = 1;
|
regs->reg3074.osd_plt_typ = VEPU541_OSD_PLT_TYPE_USERDEF;
|
} else {
|
regs->reg3074.osd_plt_cks = 0;
|
regs->reg3074.osd_plt_typ = VEPU541_OSD_PLT_TYPE_DEFAULT;
|
}
|
|
regs->reg3074.osd_e = 0;
|
regs->reg3072.osd_lu_inv_en = 0;
|
regs->reg3072.osd_ch_inv_en = 0;
|
regs->reg3072.osd_lu_inv_msk = 0;
|
regs->reg3072.osd_ch_inv_msk = 0;
|
|
RK_U32 num = osd.num_region;
|
RK_U32 k = 0;
|
MppEncOSDRegion2 *region = osd.region;
|
MppEncOSDRegion2 *tmp = region;
|
|
for (k = 0; k < num; k++, tmp++) {
|
regs->reg3074.osd_e |= tmp->enable << k;
|
regs->reg3072.osd_lu_inv_en |= (tmp->inverse) ? (1 << k) : 0;
|
regs->reg3072.osd_ch_inv_en |= (tmp->inverse) ? (1 << k) : 0;
|
|
if (tmp->enable && tmp->num_mb_x && tmp->num_mb_y) {
|
Vepu580OsdPos *pos = ®s->osd_pos[k];
|
size_t blk_len = tmp->num_mb_x * tmp->num_mb_y * 256;
|
RK_S32 fd = -1;
|
size_t buf_size = 0;
|
|
pos->osd_lt_x = tmp->start_mb_x;
|
pos->osd_lt_y = tmp->start_mb_y;
|
pos->osd_rb_x = tmp->start_mb_x + tmp->num_mb_x - 1;
|
pos->osd_rb_y = tmp->start_mb_y + tmp->num_mb_y - 1;
|
|
buf_size = mpp_buffer_get_size(tmp->buf);
|
fd = mpp_buffer_get_fd(tmp->buf);
|
if (fd < 0) {
|
mpp_err_f("invalid osd buffer fd %d\n", fd);
|
return MPP_NOK;
|
}
|
regs->osd_addr[k] = fd;
|
|
if (tmp->buf_offset) {
|
if (reg_cfg)
|
mpp_dev_multi_offset_update(reg_cfg, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset);
|
else
|
mpp_dev_set_reg_offset(dev, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset);
|
}
|
|
/* There should be enough buffer and offset should be 16B aligned */
|
if (buf_size < tmp->buf_offset + blk_len ||
|
(tmp->buf_offset & 0xf)) {
|
mpp_err_f("invalid osd cfg: %d x:y:w:h:off %d:%d:%d:%d:%x size %x\n",
|
k, tmp->start_mb_x, tmp->start_mb_y,
|
tmp->num_mb_x, tmp->num_mb_y, tmp->buf_offset, buf_size);
|
}
|
}
|
}
|
|
SET_OSD_INV_THR(0, regs->reg3073, region);
|
SET_OSD_INV_THR(1, regs->reg3073, region);
|
SET_OSD_INV_THR(2, regs->reg3073, region);
|
SET_OSD_INV_THR(3, regs->reg3073, region);
|
SET_OSD_INV_THR(4, regs->reg3073, region);
|
SET_OSD_INV_THR(5, regs->reg3073, region);
|
SET_OSD_INV_THR(6, regs->reg3073, region);
|
SET_OSD_INV_THR(7, regs->reg3073, region);
|
|
return MPP_OK;
|
}
|
