/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "vdpu34x_com"
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#include <string.h>
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#include "mpp_log.h"
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#include "mpp_buffer.h"
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#include "mpp_common.h"
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#include "vdpu34x_com.h"
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static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
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[RCB_INTRA_ROW] = 6, /* RCB_INTRA_ROW_COEF */
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[RCB_TRANSD_ROW] = 1, /* RCB_TRANSD_ROW_COEF */
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[RCB_TRANSD_COL] = 1, /* RCB_TRANSD_COL_COEF */
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[RCB_STRMD_ROW] = 3, /* RCB_STRMD_ROW_COEF */
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[RCB_INTER_ROW] = 6, /* RCB_INTER_ROW_COEF */
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[RCB_INTER_COL] = 3, /* RCB_INTER_COL_COEF */
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[RCB_DBLK_ROW] = 22, /* RCB_DBLK_ROW_COEF */
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[RCB_SAO_ROW] = 6, /* RCB_SAO_ROW_COEF */
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[RCB_FBC_ROW] = 11, /* RCB_FBC_ROW_COEF */
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[RCB_FILT_COL] = 67, /* RCB_FILT_COL_COEF */
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};
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static RK_S32 update_size_offset(Vdpu34xRcbInfo *info, RK_U32 reg,
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RK_S32 offset, RK_S32 len, RK_S32 idx)
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{
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RK_S32 buf_size = 0;
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buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
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info[idx].reg = reg;
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info[idx].offset = offset;
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info[idx].size = buf_size;
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return buf_size;
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}
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RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height)
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{
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RK_S32 offset = 0;
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offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);
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offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);
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offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);
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offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);
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offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);
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offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);
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offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);
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/* col rcb */
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offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);
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offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);
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offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);
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return offset;
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}
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void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info)
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{
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MppDevRegOffsetCfg trans_cfg;
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RK_S32 fd = mpp_buffer_get_fd(buf);
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reg->reg139_rcb_dblk_base = fd;
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reg->reg133_rcb_intra_base = fd;
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reg->reg134_rcb_transd_row_base = fd;
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reg->reg136_rcb_streamd_row_base = fd;
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reg->reg137_rcb_inter_row_base = fd;
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reg->reg140_rcb_sao_base = fd;
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reg->reg141_rcb_fbc_base = fd;
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reg->reg135_rcb_transd_col_base = fd;
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reg->reg138_rcb_inter_col_base = fd;
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reg->reg142_rcb_filter_col_base = fd;
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if (info[RCB_DBLK_ROW].offset) {
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trans_cfg.reg_idx = 139;
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trans_cfg.offset = info[RCB_DBLK_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_INTRA_ROW].offset) {
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trans_cfg.reg_idx = 133;
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trans_cfg.offset = info[RCB_INTRA_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_TRANSD_ROW].offset) {
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trans_cfg.reg_idx = 134;
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trans_cfg.offset = info[RCB_TRANSD_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_STRMD_ROW].offset) {
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trans_cfg.reg_idx = 136;
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trans_cfg.offset = info[RCB_STRMD_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_INTER_ROW].offset) {
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trans_cfg.reg_idx = 137;
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trans_cfg.offset = info[RCB_INTER_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_SAO_ROW].offset) {
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trans_cfg.reg_idx = 140;
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trans_cfg.offset = info[RCB_SAO_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_FBC_ROW].offset) {
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trans_cfg.reg_idx = 141;
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trans_cfg.offset = info[RCB_FBC_ROW].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_TRANSD_COL].offset) {
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trans_cfg.reg_idx = 135;
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trans_cfg.offset = info[RCB_TRANSD_COL].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_INTER_COL].offset) {
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trans_cfg.reg_idx = 138;
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trans_cfg.offset = info[RCB_INTER_COL].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (info[RCB_FILT_COL].offset) {
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trans_cfg.reg_idx = 142;
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trans_cfg.offset = info[RCB_FILT_COL].offset;
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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}
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RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b)
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{
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RK_S32 val = 0;
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Vdpu34xRcbInfo *p0 = (Vdpu34xRcbInfo *)a;
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Vdpu34xRcbInfo *p1 = (Vdpu34xRcbInfo *)b;
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val = (p0->size > p1->size) ? -1 : 1;
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return val;
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}
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void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta)
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{
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com->reg011.pix_range_detection_e = 1;
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memset(sta, 0, sizeof(*sta));
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sta->reg256.axi_perf_work_e = 1;
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sta->reg256.axi_perf_clr_e = 1;
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sta->reg256.axi_cnt_type = 1;
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sta->reg257.addr_align_type = 1;
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/* set hurry */
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sta->reg270.axi_rd_hurry_level = 3;
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sta->reg270.axi_wr_hurry_level = 1;
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sta->reg270.axi_wr_qos = 1;
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sta->reg270.axi_rd_qos = 3;
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sta->reg270.bus2mc_buffer_qos_level = 255;
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sta->reg271_wr_wait_cycle_qos = 0;
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}
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