/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __H265E_SYNTAX_NEW_H__
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#define __H265E_SYNTAX_NEW_H__
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#include "mpp_rc.h"
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#include "h265_syntax.h"
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#include "rc.h"
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typedef struct H265PicEntry_t {
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RK_U8 slot_idx;
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} H265ePicEntry;
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typedef struct H265ePicParams_t {
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RK_U16 pic_width;
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RK_U16 pic_height;
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RK_U16 hor_stride;
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RK_U16 ver_stride;
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RK_U16 pic_ofsty;
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RK_U16 pic_oftx;
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RK_U32 mpp_format;
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union {
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struct {
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RK_U16 chroma_format_idc : 2;
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RK_U16 separate_colour_plane_flag : 1;
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RK_U16 bit_depth_luma_minus8 : 3;
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RK_U16 bit_depth_chroma_minus8 : 3;
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RK_U16 log2_max_pic_order_cnt_lsb_minus4 : 4;
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RK_U16 NoPicReorderingFlag : 1;
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RK_U16 NoBiPredFlag : 1;
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RK_U16 ReservedBits1 : 1;
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};
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RK_U16 wFormatAndSequenceInfoFlags;
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};
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RK_U8 sps_max_dec_pic_buffering_minus1;
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RK_U8 log2_min_luma_coding_block_size_minus3;
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RK_U8 log2_diff_max_min_luma_coding_block_size;
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RK_U8 log2_min_transform_block_size_minus2;
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RK_U8 log2_diff_max_min_transform_block_size;
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RK_U8 max_transform_hierarchy_depth_inter;
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RK_U8 max_transform_hierarchy_depth_intra;
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RK_U8 num_short_term_ref_pic_sets;
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RK_U8 num_long_term_ref_pics_sps;
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RK_U8 num_ref_idx_l0_default_active_minus1;
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RK_U8 num_ref_idx_l1_default_active_minus1;
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RK_S8 init_qp_minus26;
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RK_U16 ReservedBits2;
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union {
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struct {
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RK_U32 scaling_list_enabled_flag : 1;
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RK_U32 amp_enabled_flag : 1;
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RK_U32 sample_adaptive_offset_enabled_flag : 1;
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RK_U32 pcm_enabled_flag : 1;
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RK_U32 pcm_sample_bit_depth_luma_minus1 : 4;
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RK_U32 pcm_sample_bit_depth_chroma_minus1 : 4;
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RK_U32 log2_min_pcm_luma_coding_block_size_minus3 : 2;
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RK_U32 log2_diff_max_min_pcm_luma_coding_block_size : 2;
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RK_U32 pcm_loop_filter_disabled_flag : 1;
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RK_U32 long_term_ref_pics_present_flag : 1;
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RK_U32 sps_temporal_mvp_enabled_flag : 1;
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RK_U32 strong_intra_smoothing_enabled_flag : 1;
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RK_U32 dependent_slice_segments_enabled_flag : 1;
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RK_U32 output_flag_present_flag : 1;
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RK_U32 num_extra_slice_header_bits : 3;
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RK_U32 sign_data_hiding_enabled_flag : 1;
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RK_U32 cabac_init_present_flag : 1;
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RK_U32 ReservedBits3 : 5;
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};
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RK_U32 CodingParamToolFlags;
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};
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union {
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struct {
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RK_U32 constrained_intra_pred_flag : 1;
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RK_U32 transform_skip_enabled_flag : 1;
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RK_U32 cu_qp_delta_enabled_flag : 1;
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RK_U32 pps_slice_chroma_qp_offsets_present_flag : 1;
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RK_U32 weighted_pred_flag : 1;
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RK_U32 weighted_bipred_flag : 1;
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RK_U32 transquant_bypass_enabled_flag : 1;
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RK_U32 tiles_enabled_flag : 1;
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RK_U32 entropy_coding_sync_enabled_flag : 1;
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RK_U32 uniform_spacing_flag : 1;
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RK_U32 loop_filter_across_tiles_enabled_flag : 1;
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RK_U32 pps_loop_filter_across_slices_enabled_flag : 1;
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RK_U32 deblocking_filter_override_enabled_flag : 1;
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RK_U32 pps_deblocking_filter_disabled_flag : 1;
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RK_U32 lists_modification_present_flag : 1;
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RK_U32 slice_segment_header_extension_present_flag : 1;
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RK_U32 ReservedBits4 : 16;
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};
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RK_U32 CodingSettingPicturePropertyFlags;
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};
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RK_S8 pps_cb_qp_offset;
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RK_S8 pps_cr_qp_offset;
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RK_U8 num_tile_columns_minus1;
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RK_U8 num_tile_rows_minus1;
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RK_S32 column_width_minus1[19];
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RK_S32 row_height_minus1[21];
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RK_U8 diff_cu_qp_delta_depth;
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RK_S8 pps_beta_offset_div2;
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RK_S8 pps_tc_offset_div2;
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RK_U8 log2_parallel_merge_level_minus2;
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RK_U32 vps_id;
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RK_U32 pps_id;
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RK_U32 sps_id;
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RK_U8 scaling_list_data_present_flag;
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} H265ePicParams;
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typedef struct H265eSlicParams_t {
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union {
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struct {
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RK_U32 sli_splt : 1;
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RK_U32 sli_splt_mode : 1;
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RK_U32 sli_splt_cpst : 1;
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RK_U32 sli_flsh : 1;
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RK_U32 cbc_init_flg : 1;
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RK_U32 mvd_l1_zero_flg : 1;
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RK_U32 merge_up_flag : 1;
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RK_U32 merge_left_flag : 1;
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RK_U32 ref_pic_lst_mdf_l0 : 1;
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RK_U32 num_refidx_act_ovrd : 1;
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RK_U32 sli_sao_chrm_flg : 1;
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RK_U32 sli_sao_luma_flg : 1;
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RK_U32 sli_tmprl_mvp_en : 1;
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RK_U32 pic_out_flg : 1;
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RK_U32 dpdnt_sli_seg_flg : 1;
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RK_U32 no_out_pri_pic : 1;
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RK_U32 sli_lp_fltr_acrs_sli : 1;
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RK_U32 sli_dblk_fltr_dis : 1;
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RK_U32 dblk_fltr_ovrd_flg : 1;
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RK_U32 col_ref_idx : 1;
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RK_U32 col_frm_l0_flg : 1;
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RK_U32 st_ref_pic_flg : 1;
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RK_U32 num_pos_pic : 1;
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RK_U32 dlt_poc_msb_prsnt0 : 1;
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RK_U32 dlt_poc_msb_prsnt1 : 1;
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RK_U32 dlt_poc_msb_prsnt2 : 1;
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RK_U32 used_by_lt_flg0 : 1;
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RK_U32 used_by_lt_flg1 : 1;
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RK_U32 used_by_lt_flg2 : 1;
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RK_U32 ReservedBits : 3;
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};
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RK_U32 CodingSliceFlags;
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};
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H265ePicEntry recon_pic;
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H265ePicEntry ref_pic;
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RK_S8 sli_tc_ofst_div2;
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RK_S8 sli_beta_ofst_div2;
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RK_S8 sli_cb_qp_ofst;
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RK_U8 sli_qp;
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RK_U8 max_mrg_cnd;
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RK_U8 lst_entry_l0;
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RK_U8 num_refidx_l1_act;
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RK_U8 num_refidx_l0_act;
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RK_U8 slice_type;
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RK_U8 slice_rsrv_flg;
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RK_U8 sli_pps_id;
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RK_U8 lt_idx_sps;
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RK_U8 num_lt_pic;
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RK_U8 st_ref_pic_idx;
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RK_U8 num_lt_sps;
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RK_U8 used_by_s0_flg;
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RK_U8 num_neg_pic;
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RK_U16 sli_poc_lsb;
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RK_U16 sli_hdr_ext_len;
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RK_U16 poc_lsb_lt0;
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RK_U16 sli_max_num_m1;
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RK_U16 sli_splt_cnum_m1;
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RK_U16 dlt_poc_msb_cycl0;
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RK_U16 dlt_poc_s0_m10;
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RK_U16 dlt_poc_s0_m11;
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RK_U16 dlt_poc_s0_m12;
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RK_U16 dlt_poc_s0_m13;
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RK_U16 poc_lsb_lt1;
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RK_U16 poc_lsb_lt2;
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RK_U16 dlt_poc_msb_cycl1;
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RK_U16 dlt_poc_msb_cycl2;
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RK_U32 sli_splt_byte;
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RK_U32 tot_poc_num;
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RK_U32 non_reference_flag;
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} H265eSlicParams;
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/*
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* Split reference frame configure to two parts
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* The first part is slice depended info like poc / frame_num, and frame
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* type and flags.
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* The other part is gop structure depended info like gop index, ref_status
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* and ref_frm_index. This part is inited from dpb gop hierarchy info.
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*/
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typedef struct UserDatas_t {
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void *plt_data;
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} UserDatas;
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typedef struct H265eSyntax_new_t {
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RK_S32 idr_request;
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H265ePicParams pp;
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H265eSlicParams sp;
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} H265eSyntax_new;
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#ifdef __cplusplus
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extern "C" {
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#endif
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RK_S32 h265e_syntax_fill(void *ctx);
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#ifdef __cplusplus
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}
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#endif
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#endif
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