// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Linaro
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*
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* Author: Jun Nie <jun.nie@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#define ZX_I2S_PROCESS_CTRL 0x04
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#define ZX_I2S_TIMING_CTRL 0x08
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#define ZX_I2S_FIFO_CTRL 0x0C
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#define ZX_I2S_FIFO_STATUS 0x10
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#define ZX_I2S_INT_EN 0x14
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#define ZX_I2S_INT_STATUS 0x18
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#define ZX_I2S_DATA 0x1C
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#define ZX_I2S_FRAME_CNTR 0x20
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#define I2S_DEAGULT_FIFO_THRES (0x10)
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#define I2S_MAX_FIFO_THRES (0x20)
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#define ZX_I2S_PROCESS_TX_EN (1 << 0)
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#define ZX_I2S_PROCESS_TX_DIS (0 << 0)
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#define ZX_I2S_PROCESS_RX_EN (1 << 1)
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#define ZX_I2S_PROCESS_RX_DIS (0 << 1)
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#define ZX_I2S_PROCESS_I2S_EN (1 << 2)
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#define ZX_I2S_PROCESS_I2S_DIS (0 << 2)
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#define ZX_I2S_TIMING_MAST (1 << 0)
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#define ZX_I2S_TIMING_SLAVE (0 << 0)
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#define ZX_I2S_TIMING_MS_MASK (1 << 0)
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#define ZX_I2S_TIMING_LOOP (1 << 1)
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#define ZX_I2S_TIMING_NOR (0 << 1)
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#define ZX_I2S_TIMING_LOOP_MASK (1 << 1)
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#define ZX_I2S_TIMING_PTNR (1 << 2)
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#define ZX_I2S_TIMING_NTPR (0 << 2)
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#define ZX_I2S_TIMING_PHASE_MASK (1 << 2)
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#define ZX_I2S_TIMING_TDM (1 << 3)
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#define ZX_I2S_TIMING_I2S (0 << 3)
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#define ZX_I2S_TIMING_TIMING_MASK (1 << 3)
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#define ZX_I2S_TIMING_LONG_SYNC (1 << 4)
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#define ZX_I2S_TIMING_SHORT_SYNC (0 << 4)
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#define ZX_I2S_TIMING_SYNC_MASK (1 << 4)
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#define ZX_I2S_TIMING_TEAK_EN (1 << 5)
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#define ZX_I2S_TIMING_TEAK_DIS (0 << 5)
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#define ZX_I2S_TIMING_TEAK_MASK (1 << 5)
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#define ZX_I2S_TIMING_STD_I2S (0 << 6)
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#define ZX_I2S_TIMING_MSB_JUSTIF (1 << 6)
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#define ZX_I2S_TIMING_LSB_JUSTIF (2 << 6)
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#define ZX_I2S_TIMING_ALIGN_MASK (3 << 6)
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#define ZX_I2S_TIMING_CHN_MASK (7 << 8)
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#define ZX_I2S_TIMING_CHN(x) ((x - 1) << 8)
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#define ZX_I2S_TIMING_LANE_MASK (3 << 11)
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#define ZX_I2S_TIMING_LANE(x) ((x - 1) << 11)
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#define ZX_I2S_TIMING_TSCFG_MASK (7 << 13)
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#define ZX_I2S_TIMING_TSCFG(x) (x << 13)
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#define ZX_I2S_TIMING_TS_WIDTH_MASK (0x1f << 16)
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#define ZX_I2S_TIMING_TS_WIDTH(x) ((x - 1) << 16)
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#define ZX_I2S_TIMING_DATA_SIZE_MASK (0x1f << 21)
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#define ZX_I2S_TIMING_DATA_SIZE(x) ((x - 1) << 21)
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#define ZX_I2S_TIMING_CFG_ERR_MASK (1 << 31)
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#define ZX_I2S_FIFO_CTRL_TX_RST (1 << 0)
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#define ZX_I2S_FIFO_CTRL_TX_RST_MASK (1 << 0)
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#define ZX_I2S_FIFO_CTRL_RX_RST (1 << 1)
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#define ZX_I2S_FIFO_CTRL_RX_RST_MASK (1 << 1)
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#define ZX_I2S_FIFO_CTRL_TX_DMA_EN (1 << 4)
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#define ZX_I2S_FIFO_CTRL_TX_DMA_DIS (0 << 4)
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#define ZX_I2S_FIFO_CTRL_TX_DMA_MASK (1 << 4)
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#define ZX_I2S_FIFO_CTRL_RX_DMA_EN (1 << 5)
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#define ZX_I2S_FIFO_CTRL_RX_DMA_DIS (0 << 5)
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#define ZX_I2S_FIFO_CTRL_RX_DMA_MASK (1 << 5)
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#define ZX_I2S_FIFO_CTRL_TX_THRES_MASK (0x1F << 8)
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#define ZX_I2S_FIFO_CTRL_RX_THRES_MASK (0x1F << 16)
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#define CLK_RAT (32 * 4)
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struct zx_i2s_info {
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struct snd_dmaengine_dai_dma_data dma_playback;
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struct snd_dmaengine_dai_dma_data dma_capture;
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struct clk *dai_wclk;
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struct clk *dai_pclk;
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void __iomem *reg_base;
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int master;
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resource_size_t mapbase;
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};
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static void zx_i2s_tx_en(void __iomem *base, bool on)
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{
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unsigned long val;
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val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
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if (on)
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val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
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else
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val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
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writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
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}
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static void zx_i2s_rx_en(void __iomem *base, bool on)
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{
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unsigned long val;
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val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
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if (on)
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val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
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else
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val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
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writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
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}
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static void zx_i2s_tx_dma_en(void __iomem *base, bool on)
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{
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unsigned long val;
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val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
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val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
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if (on)
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val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
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else
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val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
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writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
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}
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static void zx_i2s_rx_dma_en(void __iomem *base, bool on)
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{
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unsigned long val;
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val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
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val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
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if (on)
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val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
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else
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val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
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writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
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}
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#define ZX_I2S_RATES \
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000| \
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SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
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#define ZX_I2S_FMTBIT \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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static int zx_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
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snd_soc_dai_set_drvdata(dai, zx_i2s);
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zx_i2s->dma_playback.addr = zx_i2s->mapbase + ZX_I2S_DATA;
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zx_i2s->dma_playback.maxburst = 16;
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zx_i2s->dma_capture.addr = zx_i2s->mapbase + ZX_I2S_DATA;
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zx_i2s->dma_capture.maxburst = 16;
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snd_soc_dai_init_dma_data(dai, &zx_i2s->dma_playback,
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&zx_i2s->dma_capture);
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return 0;
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}
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static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned long val;
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val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
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val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
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ZX_I2S_TIMING_TEAK_MASK | ZX_I2S_TIMING_SYNC_MASK |
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ZX_I2S_TIMING_MS_MASK);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
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break;
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default:
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dev_err(cpu_dai->dev, "Unknown i2s timing\n");
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Codec is master, and I2S is slave. */
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i2s->master = 0;
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val |= ZX_I2S_TIMING_SLAVE;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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/* Codec is slave, and I2S is master. */
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i2s->master = 1;
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val |= ZX_I2S_TIMING_MAST;
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break;
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default:
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dev_err(cpu_dai->dev, "Unknown master/slave format\n");
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return -EINVAL;
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}
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writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
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return 0;
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}
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static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *socdai)
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{
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struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
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struct snd_dmaengine_dai_dma_data *dma_data;
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unsigned int lane, ch_num, len, ret = 0;
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unsigned int ts_width = 32;
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unsigned long val;
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unsigned long chn_cfg;
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dma_data = snd_soc_dai_get_dma_data(socdai, substream);
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dma_data->addr_width = ts_width >> 3;
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val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
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val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
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ZX_I2S_TIMING_LANE_MASK | ZX_I2S_TIMING_CHN_MASK |
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ZX_I2S_TIMING_TSCFG_MASK);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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len = 16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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len = 24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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len = 32;
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break;
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default:
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dev_err(socdai->dev, "Unknown data format\n");
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return -EINVAL;
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}
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val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
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ch_num = params_channels(params);
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switch (ch_num) {
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case 1:
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lane = 1;
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chn_cfg = 2;
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break;
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case 2:
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case 4:
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case 6:
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case 8:
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lane = ch_num / 2;
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chn_cfg = 3;
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break;
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default:
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dev_err(socdai->dev, "Not support channel num %d\n", ch_num);
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return -EINVAL;
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}
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val |= ZX_I2S_TIMING_LANE(lane);
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val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
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val |= ZX_I2S_TIMING_CHN(ch_num);
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writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
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if (i2s->master)
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ret = clk_set_rate(i2s->dai_wclk,
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params_rate(params) * ch_num * CLK_RAT);
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return ret;
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}
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static int zx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
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int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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if (capture)
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zx_i2s_rx_dma_en(zx_i2s->reg_base, true);
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else
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zx_i2s_tx_dma_en(zx_i2s->reg_base, true);
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fallthrough;
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (capture)
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zx_i2s_rx_en(zx_i2s->reg_base, true);
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else
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zx_i2s_tx_en(zx_i2s->reg_base, true);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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if (capture)
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zx_i2s_rx_dma_en(zx_i2s->reg_base, false);
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else
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zx_i2s_tx_dma_en(zx_i2s->reg_base, false);
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fallthrough;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (capture)
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zx_i2s_rx_en(zx_i2s->reg_base, false);
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else
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zx_i2s_tx_en(zx_i2s->reg_base, false);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int zx_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
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int ret;
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ret = clk_prepare_enable(zx_i2s->dai_wclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(zx_i2s->dai_pclk);
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if (ret) {
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clk_disable_unprepare(zx_i2s->dai_wclk);
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return ret;
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}
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return ret;
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}
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static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
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clk_disable_unprepare(zx_i2s->dai_wclk);
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clk_disable_unprepare(zx_i2s->dai_pclk);
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}
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static const struct snd_soc_dai_ops zx_i2s_dai_ops = {
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.trigger = zx_i2s_trigger,
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.hw_params = zx_i2s_hw_params,
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.set_fmt = zx_i2s_set_fmt,
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.startup = zx_i2s_startup,
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.shutdown = zx_i2s_shutdown,
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};
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static const struct snd_soc_component_driver zx_i2s_component = {
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.name = "zx-i2s",
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};
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static struct snd_soc_dai_driver zx_i2s_dai = {
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.name = "zx-i2s-dai",
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.id = 0,
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.probe = zx_i2s_dai_probe,
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.playback = {
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.channels_min = 1,
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.channels_max = 8,
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.rates = ZX_I2S_RATES,
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.formats = ZX_I2S_FMTBIT,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = ZX_I2S_RATES,
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.formats = ZX_I2S_FMTBIT,
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},
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.ops = &zx_i2s_dai_ops,
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};
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static int zx_i2s_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct zx_i2s_info *zx_i2s;
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int ret;
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zx_i2s = devm_kzalloc(&pdev->dev, sizeof(*zx_i2s), GFP_KERNEL);
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if (!zx_i2s)
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return -ENOMEM;
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zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
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if (IS_ERR(zx_i2s->dai_wclk)) {
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dev_err(&pdev->dev, "Fail to get wclk\n");
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return PTR_ERR(zx_i2s->dai_wclk);
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}
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zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(zx_i2s->dai_pclk)) {
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dev_err(&pdev->dev, "Fail to get pclk\n");
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return PTR_ERR(zx_i2s->dai_pclk);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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zx_i2s->mapbase = res->start;
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zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(zx_i2s->reg_base)) {
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dev_err(&pdev->dev, "ioremap failed!\n");
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return PTR_ERR(zx_i2s->reg_base);
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}
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writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL);
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platform_set_drvdata(pdev, zx_i2s);
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ret = devm_snd_soc_register_component(&pdev->dev, &zx_i2s_component,
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&zx_i2s_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
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return ret;
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}
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
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if (ret)
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dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
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return ret;
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}
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static const struct of_device_id zx_i2s_dt_ids[] = {
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{ .compatible = "zte,zx296702-i2s", },
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{}
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};
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MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
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static struct platform_driver i2s_driver = {
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.probe = zx_i2s_probe,
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.driver = {
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.name = "zx-i2s",
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.of_match_table = zx_i2s_dt_ids,
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},
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};
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module_platform_driver(i2s_driver);
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MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
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MODULE_DESCRIPTION("ZTE I2S SoC DAI");
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MODULE_LICENSE("GPL");
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