/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef _MESON_AXG_FIFO_H
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#define _MESON_AXG_FIFO_H
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struct clk;
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struct platform_device;
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struct reg_field;
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struct regmap;
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struct regmap_field;
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struct reset_control;
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struct snd_soc_component_driver;
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struct snd_soc_dai;
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struct snd_soc_dai_driver;
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struct snd_soc_pcm_runtime;
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#define AXG_FIFO_CH_MAX 128
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#define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \
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SNDRV_PCM_RATE_8000_192000)
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#define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE | \
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SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
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#define AXG_FIFO_BURST 8
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#define FIFO_INT_ADDR_FINISH BIT(0)
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#define FIFO_INT_ADDR_INT BIT(1)
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#define FIFO_INT_COUNT_REPEAT BIT(2)
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#define FIFO_INT_COUNT_ONCE BIT(3)
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#define FIFO_INT_FIFO_ZERO BIT(4)
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#define FIFO_INT_FIFO_DEPTH BIT(5)
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#define FIFO_INT_MASK GENMASK(7, 0)
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#define FIFO_CTRL0 0x00
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#define CTRL0_DMA_EN BIT(31)
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#define CTRL0_INT_EN(x) ((x) << 16)
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#define CTRL0_SEL_MASK GENMASK(2, 0)
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#define CTRL0_SEL_SHIFT 0
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#define FIFO_CTRL1 0x04
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#define CTRL1_INT_CLR(x) ((x) << 0)
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#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
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#define CTRL1_STATUS2_SEL(x) ((x) << 8)
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#define STATUS2_SEL_DDR_READ 0
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#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
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#define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
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#define FIFO_START_ADDR 0x08
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#define FIFO_FINISH_ADDR 0x0c
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#define FIFO_INT_ADDR 0x10
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#define FIFO_STATUS1 0x14
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#define STATUS1_INT_STS(x) ((x) << 0)
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#define FIFO_STATUS2 0x18
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#define FIFO_INIT_ADDR 0x24
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#define FIFO_CTRL2 0x28
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struct axg_fifo {
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struct regmap *map;
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struct clk *pclk;
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struct reset_control *arb;
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struct regmap_field *field_threshold;
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unsigned int depth;
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int irq;
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};
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struct axg_fifo_match_data {
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const struct snd_soc_component_driver *component_drv;
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struct snd_soc_dai_driver *dai_drv;
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struct reg_field field_threshold;
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};
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int axg_fifo_pcm_open(struct snd_soc_component *component,
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struct snd_pcm_substream *ss);
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int axg_fifo_pcm_close(struct snd_soc_component *component,
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struct snd_pcm_substream *ss);
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int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *ss,
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struct snd_pcm_hw_params *params);
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int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *ss,
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struct snd_pcm_hw_params *params);
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int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
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struct snd_pcm_substream *ss);
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snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
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struct snd_pcm_substream *ss);
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int axg_fifo_pcm_trigger(struct snd_soc_component *component,
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struct snd_pcm_substream *ss, int cmd);
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int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
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int axg_fifo_probe(struct platform_device *pdev);
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#endif /* _MESON_AXG_FIFO_H */
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