/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DDK750_SII164_H__
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#define DDK750_SII164_H__
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#define USE_DVICHIP
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/* Hot Plug detection mode structure */
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enum sii164_hot_plug_mode {
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SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit
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* (always high).
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*/
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SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */
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SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */
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SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */
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};
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/* Silicon Image SiI164 chip prototype */
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long sii164InitChip(unsigned char edgeSelect,
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unsigned char busSelect,
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unsigned char dualEdgeClkSelect,
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unsigned char hsyncEnable,
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unsigned char vsyncEnable,
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unsigned char deskewEnable,
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unsigned char deskewSetting,
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unsigned char continuousSyncEnable,
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unsigned char pllFilterEnable,
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unsigned char pllFilterValue);
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unsigned short sii164GetVendorID(void);
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unsigned short sii164GetDeviceID(void);
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#ifdef SII164_FULL_FUNCTIONS
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void sii164ResetChip(void);
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char *sii164GetChipString(void);
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void sii164SetPower(unsigned char powerUp);
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void sii164EnableHotPlugDetection(unsigned char enableHotPlug);
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unsigned char sii164IsConnected(void);
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unsigned char sii164CheckInterrupt(void);
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void sii164ClearInterrupt(void);
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#endif
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/*
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* below register definition is used for
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* Silicon Image SiI164 DVI controller chip
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*/
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/*
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* Vendor ID registers
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*/
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#define SII164_VENDOR_ID_LOW 0x00
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#define SII164_VENDOR_ID_HIGH 0x01
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/*
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* Device ID registers
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*/
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#define SII164_DEVICE_ID_LOW 0x02
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#define SII164_DEVICE_ID_HIGH 0x03
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/*
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* Device Revision
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*/
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#define SII164_DEVICE_REVISION 0x04
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/*
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* Frequency Limitation registers
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*/
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#define SII164_FREQUENCY_LIMIT_LOW 0x06
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#define SII164_FREQUENCY_LIMIT_HIGH 0x07
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/*
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* Power Down and Input Signal Configuration registers
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*/
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#define SII164_CONFIGURATION 0x08
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/* Power down (PD) */
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#define SII164_CONFIGURATION_POWER_DOWN 0x00
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#define SII164_CONFIGURATION_POWER_NORMAL 0x01
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#define SII164_CONFIGURATION_POWER_MASK 0x01
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/* Input Edge Latch Select (EDGE) */
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#define SII164_CONFIGURATION_LATCH_FALLING 0x00
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#define SII164_CONFIGURATION_LATCH_RISING 0x02
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/* Bus Select (BSEL) */
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#define SII164_CONFIGURATION_BUS_12BITS 0x00
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#define SII164_CONFIGURATION_BUS_24BITS 0x04
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/* Dual Edge Clock Select (DSEL) */
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#define SII164_CONFIGURATION_CLOCK_SINGLE 0x00
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#define SII164_CONFIGURATION_CLOCK_DUAL 0x08
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/* Horizontal Sync Enable (HEN) */
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#define SII164_CONFIGURATION_HSYNC_FORCE_LOW 0x00
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#define SII164_CONFIGURATION_HSYNC_AS_IS 0x10
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/* Vertical Sync Enable (VEN) */
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#define SII164_CONFIGURATION_VSYNC_FORCE_LOW 0x00
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#define SII164_CONFIGURATION_VSYNC_AS_IS 0x20
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/*
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* Detection registers
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*/
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#define SII164_DETECT 0x09
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/* Monitor Detect Interrupt (MDI) */
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#define SII164_DETECT_MONITOR_STATE_CHANGE 0x00
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#define SII164_DETECT_MONITOR_STATE_NO_CHANGE 0x01
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#define SII164_DETECT_MONITOR_STATE_CLEAR 0x01
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#define SII164_DETECT_MONITOR_STATE_MASK 0x01
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/* Hot Plug detect Input (HTPLG) */
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#define SII164_DETECT_HOT_PLUG_STATUS_OFF 0x00
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#define SII164_DETECT_HOT_PLUG_STATUS_ON 0x02
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#define SII164_DETECT_HOT_PLUG_STATUS_MASK 0x02
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/* Receiver Sense (RSEN) */
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#define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED 0x00
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#define SII164_DETECT_RECEIVER_SENSE_DETECTED 0x04
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/* Interrupt Generation Method (TSEL) */
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#define SII164_DETECT_INTERRUPT_BY_RSEN_PIN 0x00
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#define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN 0x08
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#define SII164_DETECT_INTERRUPT_MASK 0x08
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/* Monitor Sense Output (MSEN) */
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#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH 0x00
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#define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI 0x10
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#define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN 0x20
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#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG 0x30
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#define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG 0x30
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/*
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* Skewing registers
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*/
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#define SII164_DESKEW 0x0A
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/* General Purpose Input (CTL[3:1]) */
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#define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK 0x0E
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/* De-skewing Enable bit (DKEN) */
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#define SII164_DESKEW_DISABLE 0x00
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#define SII164_DESKEW_ENABLE 0x10
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/* De-skewing Setting (DK[3:1])*/
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#define SII164_DESKEW_1_STEP 0x00
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#define SII164_DESKEW_2_STEP 0x20
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#define SII164_DESKEW_3_STEP 0x40
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#define SII164_DESKEW_4_STEP 0x60
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#define SII164_DESKEW_5_STEP 0x80
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#define SII164_DESKEW_6_STEP 0xA0
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#define SII164_DESKEW_7_STEP 0xC0
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#define SII164_DESKEW_8_STEP 0xE0
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/*
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* User Configuration Data registers (CFG 7:0)
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*/
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#define SII164_USER_CONFIGURATION 0x0B
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/*
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* PLL registers
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*/
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#define SII164_PLL 0x0C
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/* PLL Filter Value (PLLF) */
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#define SII164_PLL_FILTER_VALUE_MASK 0x0E
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/* PLL Filter Enable (PFEN) */
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#define SII164_PLL_FILTER_DISABLE 0x00
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#define SII164_PLL_FILTER_ENABLE 0x01
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/* Sync Continuous (SCNT) */
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#define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE 0x00
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#define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE 0x80
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#endif
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