/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DDK750_DISPLAY_H__
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#define DDK750_DISPLAY_H__
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/*
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* panel path select
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* 80000[29:28]
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*/
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#define PNL_2_OFFSET 0
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#define PNL_2_MASK (3 << PNL_2_OFFSET)
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#define PNL_2_USAGE (PNL_2_MASK << 16)
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#define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE)
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#define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE)
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/*
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* primary timing & plane enable bit
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* 1: 80000[8] & 80000[2] on
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* 0: both off
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*/
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#define PRI_TP_OFFSET 4
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#define PRI_TP_MASK BIT(PRI_TP_OFFSET)
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#define PRI_TP_USAGE (PRI_TP_MASK << 16)
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#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
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#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
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/*
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* panel sequency status
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* 80000[27:24]
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*/
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#define PNL_SEQ_OFFSET 6
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#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
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#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
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#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
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#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
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/*
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* dual digital output
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* 80000[19]
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*/
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#define DUAL_TFT_OFFSET 8
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#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
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#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
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#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
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#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
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/*
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* secondary timing & plane enable bit
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* 1:80200[8] & 80200[2] on
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* 0: both off
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*/
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#define SEC_TP_OFFSET 5
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#define SEC_TP_MASK BIT(SEC_TP_OFFSET)
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#define SEC_TP_USAGE (SEC_TP_MASK << 16)
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#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
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#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
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/*
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* crt path select
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* 80200[19:18]
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*/
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#define CRT_2_OFFSET 2
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#define CRT_2_MASK (3 << CRT_2_OFFSET)
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#define CRT_2_USAGE (CRT_2_MASK << 16)
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#define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
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#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
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/*
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* DAC affect both DVI and DSUB
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* 4[20]
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*/
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#define DAC_OFFSET 7
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#define DAC_MASK BIT(DAC_OFFSET)
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#define DAC_USAGE (DAC_MASK << 16)
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#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
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#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
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/*
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* DPMS only affect D-SUB head
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* 0[31:30]
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*/
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#define DPMS_OFFSET 9
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#define DPMS_MASK (3 << DPMS_OFFSET)
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#define DPMS_USAGE (DPMS_MASK << 16)
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#define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE)
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#define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE)
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/*
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* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
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* CRT means crt path DSUB
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*/
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enum disp_output {
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do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
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do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
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do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
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do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
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/*
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* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
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* do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
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*/
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do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
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do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
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};
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void ddk750_set_logical_disp_out(enum disp_output output);
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#endif
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