/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#ifndef __RTL8712_SYSCFG_BITDEF_H__
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#define __RTL8712_SYSCFG_BITDEF_H__
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/*SYS_PWR_CTRL*/
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/*SRCTRL0*/
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/*SRCTRL1*/
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/*SYS_CLKR*/
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/*SYS_IOS_CTRL*/
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#define iso_LDR2RP_SHT 8 /* EE Loader to Retention Path*/
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#define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
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/*SYS_CTRL*/
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#define FEN_DIO_SDIO_SHT 0
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#define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)
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#define FEN_SDIO_SHT 1
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#define FEN_SDIO BIT(FEN_SDIO_SHT)
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#define FEN_USBA_SHT 2
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#define FEN_USBA BIT(FEN_USBA_SHT)
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#define FEN_UPLL_SHT 3
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#define FEN_UPLL BIT(FEN_UPLL_SHT)
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#define FEN_USBD_SHT 4
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#define FEN_USBD BIT(FEN_USBD_SHT)
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#define FEN_DIO_PCIE_SHT 5
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#define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)
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#define FEN_PCIEA_SHT 6
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#define FEN_PCIEA BIT(FEN_PCIEA_SHT)
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#define FEN_PPLL_SHT 7
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#define FEN_PPLL BIT(FEN_PPLL_SHT)
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#define FEN_PCIED_SHT 8
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#define FEN_PCIED BIT(FEN_PCIED_SHT)
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#define FEN_CPUEN_SHT 10
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#define FEN_CPUEN BIT(FEN_CPUEN_SHT)
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#define FEN_DCORE_SHT 11
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#define FEN_DCORE BIT(FEN_DCORE_SHT)
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#define FEN_ELDR_SHT 12
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#define FEN_ELDR BIT(FEN_ELDR_SHT)
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#define PWC_DV2LDR_SHT 13
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#define PWC_DV2LDR BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/
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/*=== SYS_CLKR ===*/
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#define SYS_CLKSEL_SHT 0
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#define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
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#define PS_CLKSEL_SHT 1
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#define PS_CLKSEL BIT(PS_CLKSEL_SHT) /*System power save
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* clock select.
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*/
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#define CPU_CLKSEL_SHT 2
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#define CPU_CLKSEL BIT(CPU_CLKSEL_SHT) /* System Clock select,
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* 1: AFE source,
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* 0: System clock(L-Bus)
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*/
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#define INT32K_EN_SHT 3
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#define INT32K_EN BIT(INT32K_EN_SHT)
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#define MACSLP_SHT 4
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#define MACSLP BIT(MACSLP_SHT)
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#define MAC_CLK_EN_SHT 11
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#define MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/
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#define SYS_CLK_EN_SHT 12
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#define SYS_CLK_EN BIT(SYS_CLK_EN_SHT)
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#define RING_CLK_EN_SHT 13
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#define RING_CLK_EN BIT(RING_CLK_EN_SHT)
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#define SWHW_SEL_SHT 14
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#define SWHW_SEL BIT(SWHW_SEL_SHT) /* Load done,
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* control path switch.
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*/
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#define FWHW_SEL_SHT 15
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#define FWHW_SEL BIT(FWHW_SEL_SHT) /* Sleep exit,
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* control path switch.
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*/
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/*9346CR*/
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#define _VPDIDX_MSK 0xFF00
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#define _VPDIDX_SHT 8
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#define _EEM_MSK 0x00C0
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#define _EEM_SHT 6
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#define _EEM0 BIT(6)
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#define _EEM1 BIT(7)
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#define _EEPROM_EN BIT(5)
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#define _9356SEL BIT(4)
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#define _EECS BIT(3)
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#define _EESK BIT(2)
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#define _EEDI BIT(1)
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#define _EEDO BIT(0)
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/*AFE_MISC*/
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#define AFE_MISC_USB_MBEN_SHT 7
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#define AFE_MISC_USB_MBEN BIT(AFE_MISC_USB_MBEN_SHT)
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#define AFE_MISC_USB_BGEN_SHT 6
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#define AFE_MISC_USB_BGEN BIT(AFE_MISC_USB_BGEN_SHT)
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#define AFE_MISC_LD12_VDAJ_SHT 4
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#define AFE_MISC_LD12_VDAJ_MSK 0X0030
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#define AFE_MISC_LD12_VDAJ BIT(AFE_MISC_LD12_VDAJ_SHT)
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#define AFE_MISC_I32_EN_SHT 3
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#define AFE_MISC_I32_EN BIT(AFE_MISC_I32_EN_SHT)
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#define AFE_MISC_E32_EN_SHT 2
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#define AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT)
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#define AFE_MISC_MBEN_SHT 1
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#define AFE_MISC_MBEN BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro
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* Block's Mbias.
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*/
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#define AFE_MISC_BGEN_SHT 0
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#define AFE_MISC_BGEN BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro
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* Block's Bandgap.
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*/
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/*--------------------------------------------------------------------------*/
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/* SPS1_CTRL bits (Offset 0x18-1E, 56bits)*/
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/*--------------------------------------------------------------------------*/
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#define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/
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#define SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/
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/*----------------------------------------------------------------------------*/
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/* LDOA15_CTRL bits (Offset 0x20, 8bits)*/
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/*----------------------------------------------------------------------------*/
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#define LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/
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/*----------------------------------------------------------------------------*/
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/* 8192S LDOV12D_CTRL bit (Offset 0x21, 8bits)*/
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/*----------------------------------------------------------------------------*/
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#define LDV12_EN BIT(0) /* Enable LDOVD12 Macro Block*/
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#define LDV12_SDBY BIT(1) /* LDOVD12 standby mode*/
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/*CLK_PS_CTRL*/
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#define _CLK_GATE_EN BIT(0)
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/* EFUSE_CTRL*/
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#define EF_FLAG BIT(31) /* Access Flag, Write:1;
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* Read:0
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*/
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#define EF_PGPD 0x70000000 /* E-fuse Program time*/
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#define EF_RDT 0x0F000000 /* E-fuse read time: in the
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* unit of cycle time
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*/
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#define EF_PDN_EN BIT(19) /* EFuse Power down enable*/
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#define ALD_EN BIT(18) /* Autoload Enable*/
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#define EF_ADDR 0x0003FF00 /* Access Address*/
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#define EF_DATA 0x000000FF /* Access Data*/
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/* EFUSE_TEST*/
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#define LDOE25_EN BIT(31) /* Enable LDOE25 Macro Block*/
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/* EFUSE_CLK_CTRL*/
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#define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/
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#define EFUSE_CLK_SEL BIT(0) /* E-Fuse Clock Select,
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* 0:500K, 1:40M
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*/
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#endif /*__RTL8712_SYSCFG_BITDEF_H__*/
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