/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PSOC_SPI_REGS_H_
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#define ASIC_REG_PSOC_SPI_REGS_H_
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/*
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*****************************************
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* PSOC_SPI (Prototype: SPI)
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*****************************************
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*/
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#define mmPSOC_SPI_CTRLR0 0xC43000
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#define mmPSOC_SPI_CTRLR1 0xC43004
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#define mmPSOC_SPI_SSIENR 0xC43008
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#define mmPSOC_SPI_MWCR 0xC4300C
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#define mmPSOC_SPI_SER 0xC43010
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#define mmPSOC_SPI_BAUDR 0xC43014
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#define mmPSOC_SPI_TXFTLR 0xC43018
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#define mmPSOC_SPI_RXFTLR 0xC4301C
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#define mmPSOC_SPI_TXFLR 0xC43020
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#define mmPSOC_SPI_RXFLR 0xC43024
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#define mmPSOC_SPI_SR 0xC43028
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#define mmPSOC_SPI_IMR 0xC4302C
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#define mmPSOC_SPI_ISR 0xC43030
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#define mmPSOC_SPI_RISR 0xC43034
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#define mmPSOC_SPI_TXOICR 0xC43038
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#define mmPSOC_SPI_RXOICR 0xC4303C
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#define mmPSOC_SPI_RXUICR 0xC43040
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#define mmPSOC_SPI_MSTICR 0xC43044
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#define mmPSOC_SPI_ICR 0xC43048
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#define mmPSOC_SPI_IDR 0xC43058
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#define mmPSOC_SPI_SSI_VERSION_ID 0xC4305C
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#define mmPSOC_SPI_DR0 0xC43060
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#define mmPSOC_SPI_DR1 0xC43064
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#define mmPSOC_SPI_DR2 0xC43068
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#define mmPSOC_SPI_DR3 0xC4306C
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#define mmPSOC_SPI_DR4 0xC43070
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#define mmPSOC_SPI_DR5 0xC43074
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#define mmPSOC_SPI_DR6 0xC43078
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#define mmPSOC_SPI_DR7 0xC4307C
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#define mmPSOC_SPI_DR8 0xC43080
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#define mmPSOC_SPI_DR9 0xC43084
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#define mmPSOC_SPI_DR10 0xC43088
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#define mmPSOC_SPI_DR11 0xC4308C
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#define mmPSOC_SPI_DR12 0xC43090
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#define mmPSOC_SPI_DR13 0xC43094
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#define mmPSOC_SPI_DR14 0xC43098
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#define mmPSOC_SPI_DR15 0xC4309C
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#define mmPSOC_SPI_DR16 0xC430A0
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#define mmPSOC_SPI_DR17 0xC430A4
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#define mmPSOC_SPI_DR18 0xC430A8
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#define mmPSOC_SPI_DR19 0xC430AC
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#define mmPSOC_SPI_DR20 0xC430B0
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#define mmPSOC_SPI_DR21 0xC430B4
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#define mmPSOC_SPI_DR22 0xC430B8
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#define mmPSOC_SPI_DR23 0xC430BC
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#define mmPSOC_SPI_DR24 0xC430C0
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#define mmPSOC_SPI_DR25 0xC430C4
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#define mmPSOC_SPI_DR26 0xC430C8
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#define mmPSOC_SPI_DR27 0xC430CC
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#define mmPSOC_SPI_DR28 0xC430D0
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#define mmPSOC_SPI_DR29 0xC430D4
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#define mmPSOC_SPI_DR30 0xC430D8
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#define mmPSOC_SPI_DR31 0xC430DC
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#define mmPSOC_SPI_DR32 0xC430E0
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#define mmPSOC_SPI_DR33 0xC430E4
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#define mmPSOC_SPI_DR34 0xC430E8
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#define mmPSOC_SPI_DR35 0xC430EC
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#define mmPSOC_SPI_RX_SAMPLE_DLY 0xC430F0
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#define mmPSOC_SPI_RSVD_1 0xC430F8
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#define mmPSOC_SPI_RSVD_2 0xC430FC
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#endif /* ASIC_REG_PSOC_SPI_REGS_H_ */
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