/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC4_QM_REGS_H_
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#define ASIC_REG_TPC4_QM_REGS_H_
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/*
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*****************************************
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* TPC4_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC4_QM_GLBL_CFG0 0xF08000
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#define mmTPC4_QM_GLBL_CFG1 0xF08004
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#define mmTPC4_QM_GLBL_PROT 0xF08008
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#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C
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#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010
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#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014
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#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018
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#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C
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#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034
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#define mmTPC4_QM_GLBL_STS0 0xF08038
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#define mmTPC4_QM_GLBL_STS1_0 0xF08040
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#define mmTPC4_QM_GLBL_STS1_1 0xF08044
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#define mmTPC4_QM_GLBL_STS1_2 0xF08048
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#define mmTPC4_QM_GLBL_STS1_3 0xF0804C
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#define mmTPC4_QM_GLBL_STS1_4 0xF08050
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#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054
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#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058
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#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C
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#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060
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#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068
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#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070
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#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074
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#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078
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#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C
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#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080
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#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084
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#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088
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#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C
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#define mmTPC4_QM_PQ_SIZE_0 0xF08090
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#define mmTPC4_QM_PQ_SIZE_1 0xF08094
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#define mmTPC4_QM_PQ_SIZE_2 0xF08098
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#define mmTPC4_QM_PQ_SIZE_3 0xF0809C
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#define mmTPC4_QM_PQ_PI_0 0xF080A0
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#define mmTPC4_QM_PQ_PI_1 0xF080A4
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#define mmTPC4_QM_PQ_PI_2 0xF080A8
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#define mmTPC4_QM_PQ_PI_3 0xF080AC
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#define mmTPC4_QM_PQ_CI_0 0xF080B0
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#define mmTPC4_QM_PQ_CI_1 0xF080B4
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#define mmTPC4_QM_PQ_CI_2 0xF080B8
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#define mmTPC4_QM_PQ_CI_3 0xF080BC
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#define mmTPC4_QM_PQ_CFG0_0 0xF080C0
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#define mmTPC4_QM_PQ_CFG0_1 0xF080C4
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#define mmTPC4_QM_PQ_CFG0_2 0xF080C8
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#define mmTPC4_QM_PQ_CFG0_3 0xF080CC
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#define mmTPC4_QM_PQ_CFG1_0 0xF080D0
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#define mmTPC4_QM_PQ_CFG1_1 0xF080D4
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#define mmTPC4_QM_PQ_CFG1_2 0xF080D8
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#define mmTPC4_QM_PQ_CFG1_3 0xF080DC
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#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0
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#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4
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#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8
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#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC
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#define mmTPC4_QM_PQ_STS0_0 0xF080F0
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#define mmTPC4_QM_PQ_STS0_1 0xF080F4
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#define mmTPC4_QM_PQ_STS0_2 0xF080F8
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#define mmTPC4_QM_PQ_STS0_3 0xF080FC
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#define mmTPC4_QM_PQ_STS1_0 0xF08100
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#define mmTPC4_QM_PQ_STS1_1 0xF08104
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#define mmTPC4_QM_PQ_STS1_2 0xF08108
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#define mmTPC4_QM_PQ_STS1_3 0xF0810C
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#define mmTPC4_QM_CQ_CFG0_0 0xF08110
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#define mmTPC4_QM_CQ_CFG0_1 0xF08114
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#define mmTPC4_QM_CQ_CFG0_2 0xF08118
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#define mmTPC4_QM_CQ_CFG0_3 0xF0811C
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#define mmTPC4_QM_CQ_CFG0_4 0xF08120
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#define mmTPC4_QM_CQ_CFG1_0 0xF08124
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#define mmTPC4_QM_CQ_CFG1_1 0xF08128
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#define mmTPC4_QM_CQ_CFG1_2 0xF0812C
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#define mmTPC4_QM_CQ_CFG1_3 0xF08130
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#define mmTPC4_QM_CQ_CFG1_4 0xF08134
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#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138
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#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C
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#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140
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#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144
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#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148
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#define mmTPC4_QM_CQ_STS0_0 0xF0814C
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#define mmTPC4_QM_CQ_STS0_1 0xF08150
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#define mmTPC4_QM_CQ_STS0_2 0xF08154
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#define mmTPC4_QM_CQ_STS0_3 0xF08158
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#define mmTPC4_QM_CQ_STS0_4 0xF0815C
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#define mmTPC4_QM_CQ_STS1_0 0xF08160
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#define mmTPC4_QM_CQ_STS1_1 0xF08164
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#define mmTPC4_QM_CQ_STS1_2 0xF08168
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#define mmTPC4_QM_CQ_STS1_3 0xF0816C
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#define mmTPC4_QM_CQ_STS1_4 0xF08170
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#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174
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#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178
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#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C
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#define mmTPC4_QM_CQ_CTL_0 0xF08180
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#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184
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#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188
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#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C
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#define mmTPC4_QM_CQ_CTL_1 0xF08190
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#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194
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#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198
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#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C
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#define mmTPC4_QM_CQ_CTL_2 0xF081A0
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#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4
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#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8
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#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC
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#define mmTPC4_QM_CQ_CTL_3 0xF081B0
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#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4
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#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8
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#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC
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#define mmTPC4_QM_CQ_CTL_4 0xF081C0
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#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4
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#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8
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#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC
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#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0
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#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4
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#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8
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#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC
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#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0
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#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4
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#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8
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#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC
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#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0
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#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4
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#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8
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#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC
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#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200
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#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204
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#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208
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#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C
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#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210
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#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214
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#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218
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#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C
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#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220
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#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304
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#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308
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#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C
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#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310
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#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314
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#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318
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#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C
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#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320
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#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324
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#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328
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#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C
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#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330
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#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334
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#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338
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#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C
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#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340
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#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344
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#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348
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#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C
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#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350
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#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354
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#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358
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#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C
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#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360
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#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364
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#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368
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#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C
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#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370
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#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374
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#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378
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#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C
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#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380
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#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384
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#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388
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#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C
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#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390
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#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394
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#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398
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#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C
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#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0
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#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4
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#define mmTPC4_QM_CP_STS_0 0xF083A8
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#define mmTPC4_QM_CP_STS_1 0xF083AC
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#define mmTPC4_QM_CP_STS_2 0xF083B0
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#define mmTPC4_QM_CP_STS_3 0xF083B4
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#define mmTPC4_QM_CP_STS_4 0xF083B8
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#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC
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#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0
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#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4
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#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8
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#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC
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#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0
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#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4
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#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8
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#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC
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#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0
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#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4
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#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8
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#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC
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#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400
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#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404
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#define mmTPC4_QM_CP_DBG_0_0 0xF08408
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#define mmTPC4_QM_CP_DBG_0_1 0xF0840C
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#define mmTPC4_QM_CP_DBG_0_2 0xF08410
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#define mmTPC4_QM_CP_DBG_0_3 0xF08414
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#define mmTPC4_QM_CP_DBG_0_4 0xF08418
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#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C
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#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420
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#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424
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#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428
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#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C
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#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430
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#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434
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#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438
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#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C
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#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440
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#define mmTPC4_QM_ARB_CFG_0 0xF08A00
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#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04
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#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08
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#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C
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#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10
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#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14
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#define mmTPC4_QM_ARB_CFG_1 0xF08A18
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98
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#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C
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#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C
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#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20
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#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28
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#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C
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#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34
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#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38
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#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C
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#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44
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#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48
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#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C
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#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50
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#define mmTPC4_QM_ARB_BASE_LO 0xF08B54
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#define mmTPC4_QM_ARB_BASE_HI 0xF08B58
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#define mmTPC4_QM_ARB_STATE_STS 0xF08B80
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#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84
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#define mmTPC4_QM_ARB_MSG_STS 0xF08B88
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#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C
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#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C
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#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0
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#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8
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#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0
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#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4
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#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8
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#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC
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#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0
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#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4
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#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8
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#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC
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#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0
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#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4
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#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8
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#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC
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#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0
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#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4
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#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8
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#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC
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#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0
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#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4
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#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8
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#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC
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#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00
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#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04
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#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08
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#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C
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#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10
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#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14
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#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18
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#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C
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#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20
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#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24
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#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28
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#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C
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#define mmTPC4_QM_CGM_CFG 0xF08C70
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#define mmTPC4_QM_CGM_STS 0xF08C74
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#define mmTPC4_QM_CGM_CFG1 0xF08C78
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#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80
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#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84
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#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90
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#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94
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#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98
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#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C
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#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0
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#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4
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#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0
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#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4
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#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8
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#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC
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#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0
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#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4
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#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8
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#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00
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#endif /* ASIC_REG_TPC4_QM_REGS_H_ */
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