/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA6_CORE_REGS_H_
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#define ASIC_REG_DMA6_CORE_REGS_H_
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/*
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*****************************************
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* DMA6_CORE (Prototype: DMA_CORE)
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*****************************************
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*/
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#define mmDMA6_CORE_CFG_0 0x5C0000
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#define mmDMA6_CORE_CFG_1 0x5C0004
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#define mmDMA6_CORE_LBW_MAX_OUTSTAND 0x5C0008
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#define mmDMA6_CORE_SRC_BASE_LO 0x5C0014
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#define mmDMA6_CORE_SRC_BASE_HI 0x5C0018
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#define mmDMA6_CORE_DST_BASE_LO 0x5C001C
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#define mmDMA6_CORE_DST_BASE_HI 0x5C0020
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#define mmDMA6_CORE_SRC_TSIZE_1 0x5C002C
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#define mmDMA6_CORE_SRC_STRIDE_1 0x5C0030
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#define mmDMA6_CORE_SRC_TSIZE_2 0x5C0034
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#define mmDMA6_CORE_SRC_STRIDE_2 0x5C0038
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#define mmDMA6_CORE_SRC_TSIZE_3 0x5C003C
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#define mmDMA6_CORE_SRC_STRIDE_3 0x5C0040
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#define mmDMA6_CORE_SRC_TSIZE_4 0x5C0044
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#define mmDMA6_CORE_SRC_STRIDE_4 0x5C0048
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#define mmDMA6_CORE_SRC_TSIZE_0 0x5C004C
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#define mmDMA6_CORE_DST_TSIZE_1 0x5C0054
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#define mmDMA6_CORE_DST_STRIDE_1 0x5C0058
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#define mmDMA6_CORE_DST_TSIZE_2 0x5C005C
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#define mmDMA6_CORE_DST_STRIDE_2 0x5C0060
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#define mmDMA6_CORE_DST_TSIZE_3 0x5C0064
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#define mmDMA6_CORE_DST_STRIDE_3 0x5C0068
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#define mmDMA6_CORE_DST_TSIZE_4 0x5C006C
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#define mmDMA6_CORE_DST_STRIDE_4 0x5C0070
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#define mmDMA6_CORE_DST_TSIZE_0 0x5C0074
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#define mmDMA6_CORE_COMMIT 0x5C0078
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#define mmDMA6_CORE_WR_COMP_WDATA 0x5C007C
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#define mmDMA6_CORE_WR_COMP_ADDR_LO 0x5C0080
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#define mmDMA6_CORE_WR_COMP_ADDR_HI 0x5C0084
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#define mmDMA6_CORE_WR_COMP_AWUSER_31_11 0x5C0088
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#define mmDMA6_CORE_TE_NUMROWS 0x5C0094
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#define mmDMA6_CORE_PROT 0x5C00B8
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#define mmDMA6_CORE_SECURE_PROPS 0x5C00F0
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#define mmDMA6_CORE_NON_SECURE_PROPS 0x5C00F4
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#define mmDMA6_CORE_RD_MAX_OUTSTAND 0x5C0100
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#define mmDMA6_CORE_RD_MAX_SIZE 0x5C0104
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#define mmDMA6_CORE_RD_ARCACHE 0x5C0108
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#define mmDMA6_CORE_RD_ARUSER_31_11 0x5C0110
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#define mmDMA6_CORE_RD_INFLIGHTS 0x5C0114
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#define mmDMA6_CORE_WR_MAX_OUTSTAND 0x5C0120
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#define mmDMA6_CORE_WR_MAX_AWID 0x5C0124
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#define mmDMA6_CORE_WR_AWCACHE 0x5C0128
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#define mmDMA6_CORE_WR_AWUSER_31_11 0x5C0130
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#define mmDMA6_CORE_WR_INFLIGHTS 0x5C0134
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#define mmDMA6_CORE_RD_RATE_LIM_CFG_0 0x5C0150
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#define mmDMA6_CORE_RD_RATE_LIM_CFG_1 0x5C0154
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#define mmDMA6_CORE_WR_RATE_LIM_CFG_0 0x5C0158
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#define mmDMA6_CORE_WR_RATE_LIM_CFG_1 0x5C015C
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#define mmDMA6_CORE_ERR_CFG 0x5C0160
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#define mmDMA6_CORE_ERR_CAUSE 0x5C0164
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#define mmDMA6_CORE_ERRMSG_ADDR_LO 0x5C0170
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#define mmDMA6_CORE_ERRMSG_ADDR_HI 0x5C0174
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#define mmDMA6_CORE_ERRMSG_WDATA 0x5C0178
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#define mmDMA6_CORE_STS0 0x5C0190
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#define mmDMA6_CORE_STS1 0x5C0194
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#define mmDMA6_CORE_RD_DBGMEM_ADD 0x5C0200
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#define mmDMA6_CORE_RD_DBGMEM_DATA_WR 0x5C0204
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#define mmDMA6_CORE_RD_DBGMEM_DATA_RD 0x5C0208
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#define mmDMA6_CORE_RD_DBGMEM_CTRL 0x5C020C
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#define mmDMA6_CORE_RD_DBGMEM_RC 0x5C0210
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#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT 0x5C0220
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#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT 0x5C0224
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#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT 0x5C0228
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#define mmDMA6_CORE_DBG_DESC_CNT 0x5C022C
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#define mmDMA6_CORE_DBG_STS 0x5C0230
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#define mmDMA6_CORE_DBG_RD_DESC_ID 0x5C0234
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#define mmDMA6_CORE_DBG_WR_DESC_ID 0x5C0238
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#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */
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