/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA3_CORE_REGS_H_
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#define ASIC_REG_DMA3_CORE_REGS_H_
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/*
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*****************************************
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* DMA3_CORE (Prototype: DMA_CORE)
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*****************************************
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*/
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#define mmDMA3_CORE_CFG_0 0x560000
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#define mmDMA3_CORE_CFG_1 0x560004
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#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008
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#define mmDMA3_CORE_SRC_BASE_LO 0x560014
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#define mmDMA3_CORE_SRC_BASE_HI 0x560018
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#define mmDMA3_CORE_DST_BASE_LO 0x56001C
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#define mmDMA3_CORE_DST_BASE_HI 0x560020
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#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C
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#define mmDMA3_CORE_SRC_STRIDE_1 0x560030
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#define mmDMA3_CORE_SRC_TSIZE_2 0x560034
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#define mmDMA3_CORE_SRC_STRIDE_2 0x560038
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#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C
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#define mmDMA3_CORE_SRC_STRIDE_3 0x560040
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#define mmDMA3_CORE_SRC_TSIZE_4 0x560044
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#define mmDMA3_CORE_SRC_STRIDE_4 0x560048
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#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C
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#define mmDMA3_CORE_DST_TSIZE_1 0x560054
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#define mmDMA3_CORE_DST_STRIDE_1 0x560058
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#define mmDMA3_CORE_DST_TSIZE_2 0x56005C
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#define mmDMA3_CORE_DST_STRIDE_2 0x560060
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#define mmDMA3_CORE_DST_TSIZE_3 0x560064
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#define mmDMA3_CORE_DST_STRIDE_3 0x560068
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#define mmDMA3_CORE_DST_TSIZE_4 0x56006C
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#define mmDMA3_CORE_DST_STRIDE_4 0x560070
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#define mmDMA3_CORE_DST_TSIZE_0 0x560074
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#define mmDMA3_CORE_COMMIT 0x560078
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#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C
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#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080
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#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084
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#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088
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#define mmDMA3_CORE_TE_NUMROWS 0x560094
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#define mmDMA3_CORE_PROT 0x5600B8
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#define mmDMA3_CORE_SECURE_PROPS 0x5600F0
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#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4
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#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100
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#define mmDMA3_CORE_RD_MAX_SIZE 0x560104
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#define mmDMA3_CORE_RD_ARCACHE 0x560108
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#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110
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#define mmDMA3_CORE_RD_INFLIGHTS 0x560114
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#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120
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#define mmDMA3_CORE_WR_MAX_AWID 0x560124
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#define mmDMA3_CORE_WR_AWCACHE 0x560128
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#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130
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#define mmDMA3_CORE_WR_INFLIGHTS 0x560134
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#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150
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#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154
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#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158
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#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C
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#define mmDMA3_CORE_ERR_CFG 0x560160
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#define mmDMA3_CORE_ERR_CAUSE 0x560164
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#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170
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#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174
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#define mmDMA3_CORE_ERRMSG_WDATA 0x560178
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#define mmDMA3_CORE_STS0 0x560190
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#define mmDMA3_CORE_STS1 0x560194
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#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200
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#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204
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#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208
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#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C
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#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210
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#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220
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#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224
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#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228
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#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C
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#define mmDMA3_CORE_DBG_STS 0x560230
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#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234
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#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238
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#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */
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