/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA2_CORE_REGS_H_
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#define ASIC_REG_DMA2_CORE_REGS_H_
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/*
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*****************************************
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* DMA2_CORE (Prototype: DMA_CORE)
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*****************************************
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*/
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#define mmDMA2_CORE_CFG_0 0x540000
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#define mmDMA2_CORE_CFG_1 0x540004
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#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008
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#define mmDMA2_CORE_SRC_BASE_LO 0x540014
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#define mmDMA2_CORE_SRC_BASE_HI 0x540018
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#define mmDMA2_CORE_DST_BASE_LO 0x54001C
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#define mmDMA2_CORE_DST_BASE_HI 0x540020
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#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C
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#define mmDMA2_CORE_SRC_STRIDE_1 0x540030
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#define mmDMA2_CORE_SRC_TSIZE_2 0x540034
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#define mmDMA2_CORE_SRC_STRIDE_2 0x540038
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#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C
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#define mmDMA2_CORE_SRC_STRIDE_3 0x540040
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#define mmDMA2_CORE_SRC_TSIZE_4 0x540044
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#define mmDMA2_CORE_SRC_STRIDE_4 0x540048
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#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C
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#define mmDMA2_CORE_DST_TSIZE_1 0x540054
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#define mmDMA2_CORE_DST_STRIDE_1 0x540058
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#define mmDMA2_CORE_DST_TSIZE_2 0x54005C
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#define mmDMA2_CORE_DST_STRIDE_2 0x540060
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#define mmDMA2_CORE_DST_TSIZE_3 0x540064
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#define mmDMA2_CORE_DST_STRIDE_3 0x540068
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#define mmDMA2_CORE_DST_TSIZE_4 0x54006C
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#define mmDMA2_CORE_DST_STRIDE_4 0x540070
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#define mmDMA2_CORE_DST_TSIZE_0 0x540074
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#define mmDMA2_CORE_COMMIT 0x540078
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#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C
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#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080
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#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084
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#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088
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#define mmDMA2_CORE_TE_NUMROWS 0x540094
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#define mmDMA2_CORE_PROT 0x5400B8
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#define mmDMA2_CORE_SECURE_PROPS 0x5400F0
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#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4
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#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100
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#define mmDMA2_CORE_RD_MAX_SIZE 0x540104
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#define mmDMA2_CORE_RD_ARCACHE 0x540108
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#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110
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#define mmDMA2_CORE_RD_INFLIGHTS 0x540114
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#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120
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#define mmDMA2_CORE_WR_MAX_AWID 0x540124
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#define mmDMA2_CORE_WR_AWCACHE 0x540128
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#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130
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#define mmDMA2_CORE_WR_INFLIGHTS 0x540134
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#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150
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#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154
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#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158
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#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C
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#define mmDMA2_CORE_ERR_CFG 0x540160
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#define mmDMA2_CORE_ERR_CAUSE 0x540164
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#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170
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#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174
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#define mmDMA2_CORE_ERRMSG_WDATA 0x540178
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#define mmDMA2_CORE_STS0 0x540190
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#define mmDMA2_CORE_STS1 0x540194
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#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200
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#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204
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#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208
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#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C
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#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210
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#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220
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#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224
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#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228
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#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C
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#define mmDMA2_CORE_DBG_STS 0x540230
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#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234
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#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238
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#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */
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