/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA1_CORE_REGS_H_
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#define ASIC_REG_DMA1_CORE_REGS_H_
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/*
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*****************************************
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* DMA1_CORE (Prototype: DMA_CORE)
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*****************************************
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*/
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#define mmDMA1_CORE_CFG_0 0x520000
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#define mmDMA1_CORE_CFG_1 0x520004
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#define mmDMA1_CORE_LBW_MAX_OUTSTAND 0x520008
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#define mmDMA1_CORE_SRC_BASE_LO 0x520014
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#define mmDMA1_CORE_SRC_BASE_HI 0x520018
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#define mmDMA1_CORE_DST_BASE_LO 0x52001C
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#define mmDMA1_CORE_DST_BASE_HI 0x520020
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#define mmDMA1_CORE_SRC_TSIZE_1 0x52002C
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#define mmDMA1_CORE_SRC_STRIDE_1 0x520030
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#define mmDMA1_CORE_SRC_TSIZE_2 0x520034
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#define mmDMA1_CORE_SRC_STRIDE_2 0x520038
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#define mmDMA1_CORE_SRC_TSIZE_3 0x52003C
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#define mmDMA1_CORE_SRC_STRIDE_3 0x520040
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#define mmDMA1_CORE_SRC_TSIZE_4 0x520044
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#define mmDMA1_CORE_SRC_STRIDE_4 0x520048
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#define mmDMA1_CORE_SRC_TSIZE_0 0x52004C
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#define mmDMA1_CORE_DST_TSIZE_1 0x520054
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#define mmDMA1_CORE_DST_STRIDE_1 0x520058
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#define mmDMA1_CORE_DST_TSIZE_2 0x52005C
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#define mmDMA1_CORE_DST_STRIDE_2 0x520060
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#define mmDMA1_CORE_DST_TSIZE_3 0x520064
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#define mmDMA1_CORE_DST_STRIDE_3 0x520068
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#define mmDMA1_CORE_DST_TSIZE_4 0x52006C
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#define mmDMA1_CORE_DST_STRIDE_4 0x520070
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#define mmDMA1_CORE_DST_TSIZE_0 0x520074
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#define mmDMA1_CORE_COMMIT 0x520078
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#define mmDMA1_CORE_WR_COMP_WDATA 0x52007C
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#define mmDMA1_CORE_WR_COMP_ADDR_LO 0x520080
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#define mmDMA1_CORE_WR_COMP_ADDR_HI 0x520084
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#define mmDMA1_CORE_WR_COMP_AWUSER_31_11 0x520088
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#define mmDMA1_CORE_TE_NUMROWS 0x520094
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#define mmDMA1_CORE_PROT 0x5200B8
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#define mmDMA1_CORE_SECURE_PROPS 0x5200F0
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#define mmDMA1_CORE_NON_SECURE_PROPS 0x5200F4
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#define mmDMA1_CORE_RD_MAX_OUTSTAND 0x520100
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#define mmDMA1_CORE_RD_MAX_SIZE 0x520104
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#define mmDMA1_CORE_RD_ARCACHE 0x520108
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#define mmDMA1_CORE_RD_ARUSER_31_11 0x520110
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#define mmDMA1_CORE_RD_INFLIGHTS 0x520114
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#define mmDMA1_CORE_WR_MAX_OUTSTAND 0x520120
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#define mmDMA1_CORE_WR_MAX_AWID 0x520124
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#define mmDMA1_CORE_WR_AWCACHE 0x520128
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#define mmDMA1_CORE_WR_AWUSER_31_11 0x520130
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#define mmDMA1_CORE_WR_INFLIGHTS 0x520134
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#define mmDMA1_CORE_RD_RATE_LIM_CFG_0 0x520150
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#define mmDMA1_CORE_RD_RATE_LIM_CFG_1 0x520154
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#define mmDMA1_CORE_WR_RATE_LIM_CFG_0 0x520158
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#define mmDMA1_CORE_WR_RATE_LIM_CFG_1 0x52015C
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#define mmDMA1_CORE_ERR_CFG 0x520160
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#define mmDMA1_CORE_ERR_CAUSE 0x520164
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#define mmDMA1_CORE_ERRMSG_ADDR_LO 0x520170
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#define mmDMA1_CORE_ERRMSG_ADDR_HI 0x520174
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#define mmDMA1_CORE_ERRMSG_WDATA 0x520178
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#define mmDMA1_CORE_STS0 0x520190
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#define mmDMA1_CORE_STS1 0x520194
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#define mmDMA1_CORE_RD_DBGMEM_ADD 0x520200
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#define mmDMA1_CORE_RD_DBGMEM_DATA_WR 0x520204
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#define mmDMA1_CORE_RD_DBGMEM_DATA_RD 0x520208
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#define mmDMA1_CORE_RD_DBGMEM_CTRL 0x52020C
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#define mmDMA1_CORE_RD_DBGMEM_RC 0x520210
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#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT 0x520220
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#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT 0x520224
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#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT 0x520228
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#define mmDMA1_CORE_DBG_DESC_CNT 0x52022C
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#define mmDMA1_CORE_DBG_STS 0x520230
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#define mmDMA1_CORE_DBG_RD_DESC_ID 0x520234
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#define mmDMA1_CORE_DBG_WR_DESC_ID 0x520238
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#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */
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