/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA0_CORE_REGS_H_
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#define ASIC_REG_DMA0_CORE_REGS_H_
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/*
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*****************************************
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* DMA0_CORE (Prototype: DMA_CORE)
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*****************************************
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*/
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#define mmDMA0_CORE_CFG_0 0x500000
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#define mmDMA0_CORE_CFG_1 0x500004
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#define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008
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#define mmDMA0_CORE_SRC_BASE_LO 0x500014
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#define mmDMA0_CORE_SRC_BASE_HI 0x500018
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#define mmDMA0_CORE_DST_BASE_LO 0x50001C
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#define mmDMA0_CORE_DST_BASE_HI 0x500020
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#define mmDMA0_CORE_SRC_TSIZE_1 0x50002C
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#define mmDMA0_CORE_SRC_STRIDE_1 0x500030
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#define mmDMA0_CORE_SRC_TSIZE_2 0x500034
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#define mmDMA0_CORE_SRC_STRIDE_2 0x500038
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#define mmDMA0_CORE_SRC_TSIZE_3 0x50003C
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#define mmDMA0_CORE_SRC_STRIDE_3 0x500040
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#define mmDMA0_CORE_SRC_TSIZE_4 0x500044
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#define mmDMA0_CORE_SRC_STRIDE_4 0x500048
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#define mmDMA0_CORE_SRC_TSIZE_0 0x50004C
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#define mmDMA0_CORE_DST_TSIZE_1 0x500054
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#define mmDMA0_CORE_DST_STRIDE_1 0x500058
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#define mmDMA0_CORE_DST_TSIZE_2 0x50005C
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#define mmDMA0_CORE_DST_STRIDE_2 0x500060
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#define mmDMA0_CORE_DST_TSIZE_3 0x500064
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#define mmDMA0_CORE_DST_STRIDE_3 0x500068
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#define mmDMA0_CORE_DST_TSIZE_4 0x50006C
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#define mmDMA0_CORE_DST_STRIDE_4 0x500070
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#define mmDMA0_CORE_DST_TSIZE_0 0x500074
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#define mmDMA0_CORE_COMMIT 0x500078
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#define mmDMA0_CORE_WR_COMP_WDATA 0x50007C
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#define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080
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#define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084
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#define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088
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#define mmDMA0_CORE_TE_NUMROWS 0x500094
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#define mmDMA0_CORE_PROT 0x5000B8
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#define mmDMA0_CORE_SECURE_PROPS 0x5000F0
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#define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4
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#define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100
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#define mmDMA0_CORE_RD_MAX_SIZE 0x500104
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#define mmDMA0_CORE_RD_ARCACHE 0x500108
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#define mmDMA0_CORE_RD_ARUSER_31_11 0x500110
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#define mmDMA0_CORE_RD_INFLIGHTS 0x500114
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#define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120
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#define mmDMA0_CORE_WR_MAX_AWID 0x500124
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#define mmDMA0_CORE_WR_AWCACHE 0x500128
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#define mmDMA0_CORE_WR_AWUSER_31_11 0x500130
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#define mmDMA0_CORE_WR_INFLIGHTS 0x500134
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#define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150
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#define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154
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#define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158
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#define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C
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#define mmDMA0_CORE_ERR_CFG 0x500160
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#define mmDMA0_CORE_ERR_CAUSE 0x500164
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#define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170
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#define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174
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#define mmDMA0_CORE_ERRMSG_WDATA 0x500178
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#define mmDMA0_CORE_STS0 0x500190
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#define mmDMA0_CORE_STS1 0x500194
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#define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200
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#define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204
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#define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208
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#define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C
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#define mmDMA0_CORE_RD_DBGMEM_RC 0x500210
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#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220
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#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224
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#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228
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#define mmDMA0_CORE_DBG_DESC_CNT 0x50022C
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#define mmDMA0_CORE_DBG_STS 0x500230
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#define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234
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#define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238
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#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */
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