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| // SPDX-License-Identifier: GPL-2.0
| /*
| * Copyright (C) 2016 Intel. All rights reserved.
| */
|
| /dts-v1/;
| #include "socfpga_arria10_socdk.dtsi"
|
| &qspi {
| status = "okay";
|
| flash0: n25q00@0 {
| #address-cells = <1>;
| #size-cells = <1>;
| compatible = "micron,mt25qu02g", "jedec,spi-nor";
| reg = <0>;
| spi-max-frequency = <100000000>;
|
| m25p,fast-read;
| cdns,page-size = <256>;
| cdns,block-size = <16>;
| cdns,read-delay = <3>;
| cdns,tshsl-ns = <50>;
| cdns,tsd2d-ns = <50>;
| cdns,tchsh-ns = <4>;
| cdns,tslch-ns = <4>;
|
| partition@qspi-boot {
| label = "Boot and fpga data";
| reg = <0x0 0x2720000>;
| };
|
| partition@qspi-rootfs {
| label = "Root Filesystem - JFFS2";
| reg = <0x2720000 0x58E0000>;
| };
| };
| };
|
|
