Device-Tree bindings for rockchip mipi dsi lcd driver
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Required properties:
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- rockchip,screen_init: Whether you need this screen initialization.
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<0>: Don't need to be initialized.
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<1>: Do need to be initialized.
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- rockchip,dsi_lane: mipi lcd data lane number.
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- rockchip,dsi_hs_clk: mipi lcd high speed clock.
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- rockchip,mipi_dsi_num: mipi lcd dsi number.
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- mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd.
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- mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd.
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- rockchip,gpios: gpio pin
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- rockchip,delay: delay the millisecond.
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- rockchip,cmd_debug : debug the cammands.
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<0>: close the debug;
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<1>: open the debug;
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- rockchip,on-cmds1: write cammand to mipi lcd.
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- rockchip,cmd_type:
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<LPDT>: close the debug;
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<HSDT>: open the debug;
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- rockchip,dsi_id: write cammand to mipi lcd(left and right).
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<0>: left dsi;
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<1>: right dsi;
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<2>: left and right dsis;
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- rockchip,cmd: cammand context.
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The first parameter was data type;
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The second parameter was index(register);
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The third and ... parameter are cammand context;
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- rockchip,cmd_delay: delay the millisecond.
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- screen-type: mipi lcd type.
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<SCREEN_DUAL_MIPI>: Dual channel mipi lcd.
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<SCREEN_MIPI>: single channel mipi lcd.
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- lvds-format:No relationship.
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- out-face: DPI color coding as follows:
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<OUT_P888>:24bit
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<OUT_P666>:18bit
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<OUT_P565>:16bit
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- hactive, vactive: display resolution
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- hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
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in pixels
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vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
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lines
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- clock-frequency: display clock in Hz
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- swap-rb :exchange of red and blue.
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- swap-rg :exchange of red and green.
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- swap-gb :exchange of green and blue.
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- hsync-active: hsync pulse is active low/high/ignored
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- vsync-active: vsync pulse is active low/high/ignored
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- de-active: data-enable pulse is active low/high/ignored
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- pixelclk-active: with
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- active high = drive pixel data on rising edge/
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sample data on falling edge
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- active low = drive pixel data on falling edge/
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sample data on rising edge
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- ignored = ignored
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- interlaced (bool): boolean to enable interlaced mode
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- doublescan (bool): boolean to enable doublescan mode
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All the optional properties that are not bool follow the following logic:
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<1>: high active
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<0>: low active
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omitted: not used on hardware
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There are different ways of describing the capabilities of a display. The
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devicetree representation corresponds to the one commonly found in datasheets
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for displays. If a display supports multiple signal timings, the native-mode
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can be specified.
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The parameters are defined as:
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+----------+-------------------------------------+----------+-------+
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| | ª | | |
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| | |vback_porch | | |
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| | « | | |
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+----------#######################################----------+-------+
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| # ª # | |
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| # | # | |
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| hback # | # hfront | hsync |
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| porch # | hactive # porch | len |
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|<-------->#<-------+--------------------------->#<-------->|<----->|
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| # | # | |
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| # |vactive # | |
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| # | # | |
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| # « # | |
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+----------#######################################----------+-------+
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| | ª | | |
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| | |vfront_porch | | |
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| | « | | |
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+----------+-------------------------------------+----------+-------+
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| | ª | | |
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| | |vsync_len | | |
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| | « | | |
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+----------+-------------------------------------+----------+-------+
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Example:
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{
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/* about mipi */
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disp_mipi_init: mipi_dsi_init{
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rockchip,screen_init = <1>;
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rockchip,dsi_lane = <4>;
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rockchip,dsi_hs_clk = <1020>;
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rockchip,mipi_dsi_num = <2>;
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};
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disp_mipi_power_ctr: mipi_power_ctr {
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mipi_lcd_rst:mipi_lcd_rst{
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rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <10>;
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};
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/*mipi_lcd_en:mipi_lcd_en {
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rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <10>;
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};*/
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};
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disp_mipi_init_cmds: screen-on-cmds {
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rockchip,cmd_debug = <0>;
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rockchip,on-cmds1 {
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rockchip,cmd_type = <LPDT>;
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rockchip,dsi_id = <2>;
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rockchip,cmd = <0x05 0x01>; //set soft reset
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rockchip,cmd_delay = <10>;
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};
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};
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disp_timings: display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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screen-type = <SCREEN_DUAL_MIPI>;
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lvds-format = <LVDS_8BIT_2>;
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out-face = <OUT_P888>;
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clock-frequency = <285000000>;
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hactive = <2560>;
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vactive = <1600>;
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hsync-len = <38>;//19
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hback-porch = <80>;//40
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hfront-porch = <246>;//123
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vsync-len = <4>;
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vback-porch = <4>;
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vfront-porch = <12>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb = <0>;
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swap-rg = <0>;
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swap-gb = <0>;
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};
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};
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};
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