Rockchip RK3399 specific extensions to the cdn Display Port with rkfb
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================================
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Required properties:
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- compatible: must be "rockchip,rk3399-cdn-dp-fb"
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- reg: physical base address of the controller and length
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- clocks: from common clock binding: handle to dp clock.
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- clock-names: from common clock binding:
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Required elements: "core-clk" "pclk" "spdif"
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- resets : a list of phandle + reset specifier pairs
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- reset-names : string reset name, must be:
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"spdif"
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- power-domains : power-domain property defined with a phandle
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to respective power domain.
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- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
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- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
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- rockchip,grf: this soc should set GRF regs, so need get grf here.
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- phys: from general PHY binding: the phandle for the PHY device.
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- extcon: extcon specifier for the Power Delivery
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- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
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-------------------------------------------------------------------------------
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Example:
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cdn_dp_fb: dp-fb@fec00000 {
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compatible = "rockchip,rk3399-cdn-dp-fb";
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reg = <0x0 0xfec00000 0x0 0x100000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
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<&cru SCLK_SPDIF_REC_DPTX>;
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clock-names = "core-clk", "pclk", "spdif";
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assigned-clocks = <&cru SCLK_DP_CORE>;
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assigned-clock-rates = <100000000>;
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power-domains = <&power RK3399_PD_HDCP>;
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phys = <&tcphy0 0>, <&tcphy1 0>;
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resets = <&cru SRST_DPTX_SPDIF_REC>;
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reset-names = "spdif";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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#sound-dai-cells = <1>;
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};
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