* Mediatek Universal Flash Storage (UFS) Host Controller
|
|
UFS nodes are defined to describe on-chip UFS hardware macro.
|
Each UFS Host Controller should have its own node.
|
|
To bind UFS PHY with UFS host controller, the controller node should
|
contain a phandle reference to UFS M-PHY node.
|
|
Required properties for UFS nodes:
|
- compatible : Compatible list, contains the following controller:
|
"mediatek,mt8183-ufshci" for MediaTek UFS host controller
|
present on MT8183 chipsets.
|
"mediatek,mt8192-ufshci" for MediaTek UFS host controller
|
present on MT8192 chipsets.
|
- reg : Address and length of the UFS register set.
|
- phys : phandle to m-phy.
|
- clocks : List of phandle and clock specifier pairs.
|
- clock-names : List of clock input name strings sorted in the same
|
order as the clocks property. "ufs" is mandatory.
|
"ufs": ufshci core control clock.
|
- freq-table-hz : Array of <min max> operating frequencies stored in the same
|
order as the clocks property. If this property is not
|
defined or a value in the array is "0" then it is assumed
|
that the frequency is set by the parent clock or a
|
fixed rate clock source.
|
- vcc-supply : phandle to VCC supply regulator node.
|
|
Example:
|
|
ufsphy: phy@11fa0000 {
|
...
|
};
|
|
ufshci@11270000 {
|
compatible = "mediatek,mt8183-ufshci";
|
reg = <0 0x11270000 0 0x2300>;
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
|
phys = <&ufsphy>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>;
|
clock-names = "ufs";
|
freq-table-hz = <0 0>;
|
|
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
|
};
|
