Davinci SPI controller device bindings
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Links on DM:
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Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
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dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
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OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
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Required properties:
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- #address-cells: number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells: should be zero.
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- compatible:
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- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
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- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
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family
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- reg: Offset and length of SPI controller register space
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- num-cs: Number of chip selects. This includes internal as well as
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GPIO chip selects.
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- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
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IP to the interrupt controller within the SoC. Possible values
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are 0 and 1. Manual says one of the two possible interrupt
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lines can be tied to the interrupt controller. Set this
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based on a specific SoC configuration.
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- interrupts: interrupt number mapped to CPU.
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- clocks: spi clk phandle
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For 66AK2G this property should be set per binding,
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Documentation/devicetree/bindings/clock/ti,sci-clk.txt
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SoC-specific Required Properties:
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The following are mandatory properties for Keystone 2 66AK2G SoCs only:
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- power-domains: Should contain a phandle to a PM domain provider node
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and an args specifier containing the SPI device id
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value. This property is as per the binding,
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Optional:
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- cs-gpios: gpio chip selects
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For example to have 3 internal CS and 2 GPIO CS, user could define
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cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
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where first three are internal CS and last two are GPIO CS.
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Optional properties for slave devices:
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SPI slave nodes can contain the following properties.
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Not all SPI Peripherals from Texas Instruments support this.
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Please check SPI peripheral documentation for a device before using these.
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- ti,spi-wdelay : delay between transmission of words
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(SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
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clock periods.
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delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
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Below is timing diagram which shows functional meaning of
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"ti,spi-wdelay" parameter.
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+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
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SPI_CLK | | | | | | | | | | | | | | | |
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+----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
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SPI_SOMI/SIMO+-----------------+ +-----------
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+----------+ word1 +---------------------------+word2
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+-----------------+ +-----------
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WDELAY
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<-------------------------->
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Example of a NOR flash slave device (n25q032) connected to DaVinci
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SPI controller device over the SPI bus.
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spi0:spi@20bf0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "ti,dm6446-spi";
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reg = <0x20BF0000 0x1000>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <0>;
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interrupts = <338>;
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clocks = <&clkspi>;
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flash: n25q032@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32";
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spi-max-frequency = <25000000>;
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reg = <0>;
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ti,spi-wdelay = <8>;
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partition@0 {
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label = "u-boot-spl";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@1 {
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label = "test";
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reg = <0x80000 0x380000>;
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};
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};
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};
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