ROCKCHIP MIPI/LVDS/TTL VIDEO COMBO PHY WITH INNO IP BLOCK
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Required properties:
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- compatible : must be one of:
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"rockchip,px30-video-phy",
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"rockchip,rk3128-video-phy",
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"rockchip,rk3368-video-phy";
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"rockchip,rk3568-video-phy";
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- reg : the address offset of register for phy and host configuration.
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- #phy-cells : must be 0. See ./phy-bindings.txt for details.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property. See ../clocks/clock-bindings.txt for details.
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- clock-names: list of clock names sorted in the same order as the clocks
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property. Must contain "ref", "pclk_phy", "pclk_host".
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- #clock-cells : from common clock binding; shall be set to 0.
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- resets : phandle to the reset of phy apb clock.
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- reset-names : should be "rst".
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- power-domains: Must contain a reference to the PM domain, if available.
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Example:
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video_phy: video-phy@ff2e0000 {
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compatible = "rockchip,px30-video-phy";
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reg = <0x0 0xff2e0000 0x0 0x10000>,
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<0x0 0xff450000 0x0 0x10000>;
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clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
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<&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
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clock-names = "ref", "pclk_phy", "pclk_host";
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#clock-cells = <0>;
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resets = <&cru SRST_MIPIDSIPHY_P>;
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reset-names = "rst";
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power-domains = <&power PX30_PD_VO>;
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#phy-cells = <0>;
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status = "disabled";
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};
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