ROCKCHIP PCIE/USB3 COMBPHY WITH INNO IP BLOCK
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Required properties:
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- compatible: Should be one of the listed compatibles:
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"rockchip,rk1808-combphy"
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- reg: Should be the address space for COMBPHY registers.
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- #phy-cells: Should be 1. The cell number is used to select the
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phy mode as defined in <dt-bindings/phy/phy.h>,
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<&combphy PHY_TYPE_USB3> for USB3 PHY
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<&combphy PHY_TYPE_PCIE> for PCIE PHY
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- clocks: The phandle to clock provider and clock specifier pair.
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- clock-names: Must be "refclk", the reference clock of COMBPHY.
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- resets: The phandle to reset controller and reset specifier pair.
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- reset-names: The string reset names, must be:
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"otg-rst", "combphy-por",
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"combphy-apb", "combphy-pipe".
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- rockchip,combphygrf: The grf for COMBPHY configuration and state
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registers.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Optional properties:
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- assigned-clocks: The phandle of COMBPHY reference clock.
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- assigned-clock-rates: The COMBPHY reference clock frequency,
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the default clock frequency is 24MHz,
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can be set to 25000000 or 50000000.
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Examples:
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combphy_grf: syscon@fe018000 {
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compatible = "rockchip,usb3phy-grf", "syscon";
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reg = <0x0 0xfe018000 0x0 0x8000>;
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};
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combphy: phy@ff380000 {
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compatible = "rockchip,rk1808-combphy";
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reg = <0x0 0xff380000 0x0 0x10000>;
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#phy-cells = <1>;
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clocks = <&cru SCLK_PCIEPHY_REF>;
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clock-names = "refclk";
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assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
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assigned-clock-rates = <25000000>;
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resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>,
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<&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>;
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reset-names = "otg-rst", "combphy-por",
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"combphy-apb", "combphy-pipe";
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rockchip,combphygrf = <&combphy_grf>;
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status = "disabled";
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};
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