hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
 
title: Microchip Sparx5 Mobile Storage Host Controller Binding
 
allOf:
  - $ref: "mmc-controller.yaml"
 
maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>
 
# Everything else is described in the common file
properties:
  compatible:
    const: microchip,dw-sparx5-sdhci
 
  reg:
    maxItems: 1
 
  interrupts:
    maxItems: 1
 
  clocks:
    maxItems: 1
    description:
      Handle to "core" clock for the sdhci controller.
 
  clock-names:
    items:
      - const: core
 
  microchip,clock-delay:
    description: Delay clock to card to meet setup time requirements.
      Each step increase by 1.25ns.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 1
    maximum: 15
 
required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
 
unevaluatedProperties: false
 
examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/microchip,sparx5.h>
    sdhci0: mmc@600800000 {
        compatible = "microchip,dw-sparx5-sdhci";
        reg = <0x00800000 0x1000>;
        pinctrl-0 = <&emmc_pins>;
        pinctrl-names = "default";
        clocks = <&clks CLK_ID_AUX1>;
        clock-names = "core";
        assigned-clocks = <&clks CLK_ID_AUX1>;
        assigned-clock-rates = <800000000>;
        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
        bus-width = <8>;
        microchip,clock-delay = <10>;
    };