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| # SPDX-License-Identifier: GPL-2.0
| %YAML 1.2
| ---
| $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
| $schema: http://devicetree.org/meta-schemas/core.yaml#
|
| title: Allwinner A10 Bus Gates Clock Device Tree Bindings
|
| maintainers:
| - Chen-Yu Tsai <wens@csie.org>
| - Maxime Ripard <mripard@kernel.org>
|
| deprecated: true
|
| properties:
| "#clock-cells":
| const: 1
| description: >
| This additional argument passed to that clock is the offset of
| the bit controlling this particular gate in the register.
|
| compatible:
| oneOf:
| - const: allwinner,sun4i-a10-gates-clk
| - const: allwinner,sun4i-a10-axi-gates-clk
| - const: allwinner,sun4i-a10-ahb-gates-clk
| - const: allwinner,sun5i-a10s-ahb-gates-clk
| - const: allwinner,sun5i-a13-ahb-gates-clk
| - const: allwinner,sun7i-a20-ahb-gates-clk
| - const: allwinner,sun6i-a31-ahb1-gates-clk
| - const: allwinner,sun8i-a23-ahb1-gates-clk
| - const: allwinner,sun9i-a80-ahb0-gates-clk
| - const: allwinner,sun9i-a80-ahb1-gates-clk
| - const: allwinner,sun9i-a80-ahb2-gates-clk
| - const: allwinner,sun4i-a10-apb0-gates-clk
| - const: allwinner,sun5i-a10s-apb0-gates-clk
| - const: allwinner,sun5i-a13-apb0-gates-clk
| - const: allwinner,sun7i-a20-apb0-gates-clk
| - const: allwinner,sun9i-a80-apb0-gates-clk
| - const: allwinner,sun8i-a83t-apb0-gates-clk
| - const: allwinner,sun4i-a10-apb1-gates-clk
| - const: allwinner,sun5i-a13-apb1-gates-clk
| - const: allwinner,sun5i-a10s-apb1-gates-clk
| - const: allwinner,sun6i-a31-apb1-gates-clk
| - const: allwinner,sun7i-a20-apb1-gates-clk
| - const: allwinner,sun8i-a23-apb1-gates-clk
| - const: allwinner,sun9i-a80-apb1-gates-clk
| - const: allwinner,sun6i-a31-apb2-gates-clk
| - const: allwinner,sun8i-a23-apb2-gates-clk
| - const: allwinner,sun8i-a83t-bus-gates-clk
| - const: allwinner,sun9i-a80-apbs-gates-clk
| - const: allwinner,sun4i-a10-dram-gates-clk
|
| - items:
| - const: allwinner,sun5i-a13-dram-gates-clk
| - const: allwinner,sun4i-a10-gates-clk
|
| - items:
| - const: allwinner,sun8i-h3-apb0-gates-clk
| - const: allwinner,sun4i-a10-gates-clk
|
| reg:
| maxItems: 1
|
| clocks:
| maxItems: 1
|
| clock-indices:
| minItems: 1
| maxItems: 64
|
| clock-output-names:
| minItems: 1
| maxItems: 64
|
| required:
| - "#clock-cells"
| - compatible
| - reg
| - clocks
| - clock-indices
| - clock-output-names
|
| additionalProperties: false
|
| examples:
| - |
| clk@1c2005c {
| #clock-cells = <1>;
| compatible = "allwinner,sun4i-a10-axi-gates-clk";
| reg = <0x01c2005c 0x4>;
| clocks = <&axi>;
| clock-indices = <0>;
| clock-output-names = "axi_dram";
| };
|
| - |
| clk@1c20060 {
| #clock-cells = <1>;
| compatible = "allwinner,sun4i-a10-ahb-gates-clk";
| reg = <0x01c20060 0x8>;
| clocks = <&ahb>;
| clock-indices = <0>, <1>,
| <2>, <3>,
| <4>, <5>, <6>,
| <7>, <8>, <9>,
| <10>, <11>, <12>,
| <13>, <14>, <16>,
| <17>, <18>, <20>,
| <21>, <22>, <23>,
| <24>, <25>, <26>,
| <32>, <33>, <34>,
| <35>, <36>, <37>,
| <40>, <41>, <43>,
| <44>, <45>,
| <46>, <47>,
| <50>, <52>;
| clock-output-names = "ahb_usb0", "ahb_ehci0",
| "ahb_ohci0", "ahb_ehci1",
| "ahb_ohci1", "ahb_ss", "ahb_dma",
| "ahb_bist", "ahb_mmc0", "ahb_mmc1",
| "ahb_mmc2", "ahb_mmc3", "ahb_ms",
| "ahb_nand", "ahb_sdram", "ahb_ace",
| "ahb_emac", "ahb_ts", "ahb_spi0",
| "ahb_spi1", "ahb_spi2", "ahb_spi3",
| "ahb_pata", "ahb_sata", "ahb_gps",
| "ahb_ve", "ahb_tvd", "ahb_tve0",
| "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
| "ahb_csi0", "ahb_csi1", "ahb_hdmi",
| "ahb_de_be0", "ahb_de_be1",
| "ahb_de_fe0", "ahb_de_fe1",
| "ahb_mp", "ahb_mali400";
| };
|
|
| - |
| clk@1c20068 {
| #clock-cells = <1>;
| compatible = "allwinner,sun4i-a10-apb0-gates-clk";
| reg = <0x01c20068 0x4>;
| clocks = <&apb0>;
| clock-indices = <0>, <1>,
| <2>, <3>,
| <5>, <6>,
| <7>, <10>;
| clock-output-names = "apb0_codec", "apb0_spdif",
| "apb0_ac97", "apb0_iis",
| "apb0_pio", "apb0_ir0",
| "apb0_ir1", "apb0_keypad";
| };
|
| ...
|
|
