# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner Memory Bus (MBUS) controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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The MBUS controller drives the MBUS that other devices in the SoC
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will use to perform DMA. It also has a register interface that
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allows to monitor and control the bandwidth and priorities for
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masters on that bus.
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Each device having to perform their DMA through the MBUS must have
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the interconnects and interconnect-names properties set to the MBUS
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controller and with "dma-mem" as the interconnect name.
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properties:
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"#interconnect-cells":
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const: 1
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description:
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The content of the cell is the MBUS ID.
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compatible:
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enum:
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- allwinner,sun5i-a13-mbus
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- allwinner,sun8i-h3-mbus
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- allwinner,sun50i-a64-mbus
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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dma-ranges:
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description:
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See section 2.3.9 of the DeviceTree Specification.
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'#address-cells': true
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'#size-cells': true
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required:
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- "#interconnect-cells"
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- compatible
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- reg
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- clocks
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- dma-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun5i-ccu.h>
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mbus: dram-controller@1c01000 {
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compatible = "allwinner,sun5i-a13-mbus";
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reg = <0x01c01000 0x1000>;
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clocks = <&ccu CLK_MBUS>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x00000000 0x40000000 0x20000000>;
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#interconnect-cells = <1>;
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};
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...
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