From dbcf296f84e5cef6a3ff0f1c469a4508f1e0fb15 Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Sun, 15 Nov 2020 15:32:39 -0800
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Subject: [PATCH] numpy/core: Define RISCV-32 support
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Helps compile on riscv32
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Upstream-Status: Submitted [https://github.com/numpy/numpy/pull/17780]
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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numpy/core/include/numpy/npy_cpu.h | 9 +++++++--
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numpy/core/include/numpy/npy_endian.h | 1 +
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2 files changed, 8 insertions(+), 2 deletions(-)
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diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h
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index 4dbf9d84e..bc41a7eda 100644
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--- a/numpy/core/include/numpy/npy_cpu.h
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+++ b/numpy/core/include/numpy/npy_cpu.h
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@@ -18,6 +18,7 @@
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* NPY_CPU_ARCEL
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* NPY_CPU_ARCEB
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* NPY_CPU_RISCV64
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+ * NPY_CPU_RISCV32
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* NPY_CPU_WASM
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*/
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#ifndef _NPY_CPUARCH_H_
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@@ -100,8 +101,12 @@
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#define NPY_CPU_ARCEL
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#elif defined(__arc__) && defined(__BIG_ENDIAN__)
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#define NPY_CPU_ARCEB
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-#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
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- #define NPY_CPU_RISCV64
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+#elif defined(__riscv)
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+ #if __riscv_xlen == 64
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+ #define NPY_CPU_RISCV64
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+ #elif __riscv_xlen == 32
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+ #define NPY_CPU_RISCV32
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+ #endif
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#elif defined(__EMSCRIPTEN__)
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/* __EMSCRIPTEN__ is defined by emscripten: an LLVM-to-Web compiler */
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#define NPY_CPU_WASM
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diff --git a/numpy/core/include/numpy/npy_endian.h b/numpy/core/include/numpy/npy_endian.h
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index aa367a002..d59484573 100644
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--- a/numpy/core/include/numpy/npy_endian.h
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+++ b/numpy/core/include/numpy/npy_endian.h
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@@ -49,6 +49,7 @@
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|| defined(NPY_CPU_PPC64LE) \
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|| defined(NPY_CPU_ARCEL) \
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|| defined(NPY_CPU_RISCV64) \
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+ || defined(NPY_CPU_RISCV32) \
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|| defined(NPY_CPU_WASM)
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#define NPY_BYTE_ORDER NPY_LITTLE_ENDIAN
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#elif defined(NPY_CPU_PPC) \
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--
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2.29.2
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