// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <max96755f.h>
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#include <video_bridge.h>
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#include <dm/of_access.h>
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#include <linux/media-bus-format.h>
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#include "rockchip_bridge.h"
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#include "rockchip_display.h"
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#include "rockchip_panel.h"
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static void max96755f_mipi_dsi_rx_config(struct max96755f_priv *priv)
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{
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struct drm_display_mode *mode = &priv->mode;
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u32 hfp, hsa, hbp, hact;
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u32 vact, vsa, vfp, vbp;
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dm_i2c_reg_clrset(priv->dev, 0x0331, NUM_LANES,
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FIELD_PREP(NUM_LANES, priv->num_lanes - 1));
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if (!priv->dpi_deskew_en)
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return;
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vact = mode->vdisplay;
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vsa = mode->vsync_end - mode->vsync_start;
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vfp = mode->vsync_start - mode->vdisplay;
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vbp = mode->vtotal - mode->vsync_end;
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hact = mode->hdisplay;
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hsa = mode->hsync_end - mode->hsync_start;
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hfp = mode->hsync_start - mode->hdisplay;
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hbp = mode->htotal - mode->hsync_end;
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dm_i2c_reg_write(priv->dev, 0x03A4, 0xc1);
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dm_i2c_reg_write(priv->dev, 0x0385, FIELD_PREP(DPI_HSYNC_WIDTH_L, hsa));
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dm_i2c_reg_write(priv->dev, 0x0386, FIELD_PREP(DPI_VYSNC_WIDTH_L, vsa));
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dm_i2c_reg_write(priv->dev, 0x0387,
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FIELD_PREP(DPI_VSYNC_WIDTH_H, (vsa >> 8)) |
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FIELD_PREP(DPI_HSYNC_WIDTH_H, (hsa >> 8)));
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dm_i2c_reg_write(priv->dev, 0x03a5, FIELD_PREP(DPI_VFP_L, vfp));
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dm_i2c_reg_write(priv->dev, 0x03a6,
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FIELD_PREP(DPI_VBP_L, vbp) |
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FIELD_PREP(DPI_VFP_H, (vfp >> 8)));
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dm_i2c_reg_write(priv->dev, 0x03a7, FIELD_PREP(DPI_VBP_H, (vbp >> 4)));
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dm_i2c_reg_write(priv->dev, 0x03a8, FIELD_PREP(DPI_VACT_L, vact));
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dm_i2c_reg_write(priv->dev, 0x03a9, FIELD_PREP(DPI_VACT_H, (vact >> 8)));
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dm_i2c_reg_write(priv->dev, 0x03aa, FIELD_PREP(DPI_HFP_L, hfp));
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dm_i2c_reg_write(priv->dev, 0x03ab,
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FIELD_PREP(DPI_HBP_L, hbp) |
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FIELD_PREP(DPI_HFP_H, (hfp >> 7)));
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dm_i2c_reg_write(priv->dev, 0x03ac, FIELD_PREP(DPI_HBP_H, (hbp >> 4)));
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dm_i2c_reg_write(priv->dev, 0x03ad, FIELD_PREP(DPI_HACT_L, hact));
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dm_i2c_reg_write(priv->dev, 0x03ae, FIELD_PREP(DPI_HACT_H, (hact >> 8)));
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}
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static void max96755f_bridge_enable(struct rockchip_bridge *bridge)
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{
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struct udevice *dev = bridge->dev;
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struct max96755f_priv *priv = dev_get_priv(dev->parent);
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max96755f_mipi_dsi_rx_config(priv);
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if (priv->split_mode) {
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dm_i2c_reg_clrset(dev->parent, 0x0010,
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RESET_ONESHOT | AUTO_LINK | LINK_CFG,
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FIELD_PREP(RESET_ONESHOT, 1) |
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FIELD_PREP(AUTO_LINK, 0) |
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FIELD_PREP(LINK_CFG, SPLITTER_MODE));
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mdelay(50);
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dm_i2c_reg_clrset(dev->parent, 0x0053,
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TX_SPLIT_MASK_B | TX_SPLIT_MASK_A | TX_STR_SEL,
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FIELD_PREP(TX_SPLIT_MASK_B, 0) |
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FIELD_PREP(TX_SPLIT_MASK_A, 1) |
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FIELD_PREP(TX_STR_SEL, 0));
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dm_i2c_reg_clrset(dev->parent, 0x0057,
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TX_SPLIT_MASK_B | TX_SPLIT_MASK_A | TX_STR_SEL,
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FIELD_PREP(TX_SPLIT_MASK_B, 1) |
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FIELD_PREP(TX_SPLIT_MASK_A, 0) |
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FIELD_PREP(TX_STR_SEL, 1));
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dm_i2c_reg_clrset(dev->parent, 0x032a,
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DV_SWP_AB | DV_CONV | DV_SPL | DV_EN,
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FIELD_PREP(DV_SWP_AB, priv->dv_swp_ab) |
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FIELD_PREP(DV_CONV, 1) |
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FIELD_PREP(DV_SPL, 1) |
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FIELD_PREP(DV_EN, 1));
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dm_i2c_reg_clrset(dev->parent, 0x0311,
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START_PORTAX | START_PORTAY,
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FIELD_PREP(START_PORTAX, 1) |
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FIELD_PREP(START_PORTAY, 1));
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dm_i2c_reg_clrset(dev->parent, 0x0002,
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VID_TX_EN_X | VID_TX_EN_Y,
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FIELD_PREP(VID_TX_EN_X, 1) |
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FIELD_PREP(VID_TX_EN_Y, 1));
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} else {
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dm_i2c_reg_clrset(dev->parent, 0x0002, VID_TX_EN_X,
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FIELD_PREP(VID_TX_EN_X, 1));
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dm_i2c_reg_clrset(dev->parent, 0x0311, START_PORTAX,
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FIELD_PREP(START_PORTAX, 1));
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}
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dm_i2c_reg_clrset(dev->parent, 0x0010, RESET_ONESHOT,
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FIELD_PREP(RESET_ONESHOT, 1));
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mdelay(100);
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}
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static void max96755f_bridge_disable(struct rockchip_bridge *bridge)
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{
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struct udevice *dev = bridge->dev;
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struct max96755f_priv *priv = dev_get_priv(dev->parent);
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dm_i2c_reg_clrset(dev->parent, 0x0002, VID_TX_EN_X,
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FIELD_PREP(VID_TX_EN_X, 0));
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if (priv->split_mode)
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dm_i2c_reg_clrset(dev->parent, 0x0010,
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AUTO_LINK | LINK_CFG,
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FIELD_PREP(AUTO_LINK, 0) |
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FIELD_PREP(LINK_CFG, LINKA));
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}
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static void max96755f_bridge_mode_set(struct rockchip_bridge *bridge,
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const struct drm_display_mode *mode)
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{
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struct udevice *dev = bridge->dev;
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struct max96755f_priv *priv = dev_get_priv(dev->parent);
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memcpy(&priv->mode, mode, sizeof(struct drm_display_mode));
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}
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static bool max96755f_bridge_detect(struct rockchip_bridge *bridge)
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{
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struct max96755f_priv *priv = dev_get_priv(bridge->dev->parent);
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if (!dm_gpio_get_value(&priv->lock_gpio))
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return false;
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return true;
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}
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static const struct rockchip_bridge_funcs max96755f_bridge_funcs = {
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.enable = max96755f_bridge_enable,
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.disable = max96755f_bridge_disable,
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.mode_set = max96755f_bridge_mode_set,
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.detect = max96755f_bridge_detect,
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};
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static int max96755f_bridge_probe(struct udevice *dev)
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{
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struct rockchip_bridge *bridge;
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struct max96755f_priv *priv = dev_get_priv(dev->parent);
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int ret;
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bridge = calloc(1, sizeof(*bridge));
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if (!bridge)
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return -ENOMEM;
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dev->driver_data = (ulong)bridge;
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bridge->dev = dev;
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bridge->funcs = &max96755f_bridge_funcs;
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priv->num_lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
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priv->dv_swp_ab = dev_read_bool(dev, "vd-swap-ab");
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priv->dpi_deskew_en = dev_read_bool(dev, "dpi-deskew-en");
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ret = gpio_request_by_name(dev, "lock-gpios", 0, &priv->lock_gpio,
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GPIOD_IS_IN);
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if (ret) {
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dev_err(dev, "failed to get lock GPIO: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct udevice_id max96755f_bridge_of_match[] = {
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{ .compatible = "maxim,max96755f-bridge", },
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{ }
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};
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U_BOOT_DRIVER(max96755f_bridge) = {
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.name = "max96755f_bridge",
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.id = UCLASS_VIDEO_BRIDGE,
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.of_match = max96755f_bridge_of_match,
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.probe = max96755f_bridge_probe,
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};
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