# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
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# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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# PBL preamble and RCW header for T1024QDS
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aa55aa55 010e0100
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# Serdes protocol 0x6F
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0810000e 00000000 00000000 00000000
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37800001 00000012 58104000 21000000
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00000000 00000000 00000000 00030810
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00000000 036c5a00 00000000 00000006
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