/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/arch/device.h>
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#include <asm/arch/tnc.h>
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int queensbay_irq_router_probe(struct udevice *dev)
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{
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struct tnc_rcba *rcba;
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u32 base;
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dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
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base &= ~MEM_BAR_EN;
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rcba = (struct tnc_rcba *)base;
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/* Make sure all internal PCI devices are using INTA */
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writel(INTA, &rcba->d02ip);
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writel(INTA, &rcba->d03ip);
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writel(INTA, &rcba->d27ip);
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writel(INTA, &rcba->d31ip);
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writel(INTA, &rcba->d23ip);
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writel(INTA, &rcba->d24ip);
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writel(INTA, &rcba->d25ip);
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writel(INTA, &rcba->d26ip);
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/*
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* Route TunnelCreek PCI device interrupt pin to PIRQ
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*
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* Since PCIe downstream ports received INTx are routed to PIRQ
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* A/B/C/D directly and not configurable, we have to route PCIe
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* root ports' INTx to PIRQ A/B/C/D as well. For other devices
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* on TunneCreek, route them to PIRQ E/F/G/H.
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*/
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writew(PIRQE, &rcba->d02ir);
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writew(PIRQF, &rcba->d03ir);
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writew(PIRQG, &rcba->d27ir);
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writew(PIRQH, &rcba->d31ir);
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writew(PIRQA, &rcba->d23ir);
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writew(PIRQB, &rcba->d24ir);
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writew(PIRQC, &rcba->d25ir);
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writew(PIRQD, &rcba->d26ir);
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return irq_router_common_init(dev);
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}
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static const struct udevice_id queensbay_irq_router_ids[] = {
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{ .compatible = "intel,queensbay-irq-router" },
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{ }
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};
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U_BOOT_DRIVER(queensbay_irq_router_drv) = {
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.name = "queensbay_intel_irq",
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.id = UCLASS_IRQ,
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.of_match = queensbay_irq_router_ids,
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.probe = queensbay_irq_router_probe,
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};
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