/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3368_H
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#define _ASM_ARCH_CRU_RK3368_H
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#include <common.h>
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/* RK3368 clock numbers */
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enum rk3368_pll_id {
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APLLB,
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APLLL,
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DPLL,
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CPLL,
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GPLL,
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NPLL,
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PLL_COUNT,
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};
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struct rk3368_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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struct rk3368_cru {
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struct rk3368_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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} pll[6];
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unsigned int reserved[0x28];
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unsigned int clksel_con[56];
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unsigned int reserved1[8];
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unsigned int clkgate_con[25];
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unsigned int reserved2[7];
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unsigned int glb_srst_fst_val;
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unsigned int glb_srst_snd_val;
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unsigned int reserved3[0x1e];
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unsigned int softrst_con[15];
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unsigned int reserved4[0x11];
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unsigned int misc_con;
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unsigned int glb_cnt_th;
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unsigned int glb_rst_con;
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unsigned int glb_rst_st;
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unsigned int reserved5[0x1c];
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unsigned int sdmmc_con[2];
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unsigned int sdio0_con[2];
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unsigned int sdio1_con[2];
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unsigned int emmc_con[2];
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};
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check_member(rk3368_cru, emmc_con[1], 0x41c);
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struct rk3368_clk_priv {
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struct rk3368_cru *cru;
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ulong armlclk_hz;
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ulong armlclk_enter_hz;
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ulong armlclk_init_hz;
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ulong armbclk_hz;
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ulong armbclk_enter_hz;
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ulong armbclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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enum {
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/* PLL CON0 */
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PLL_NR_SHIFT = 8,
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PLL_NR_MASK = GENMASK(13, 8),
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PLL_OD_SHIFT = 0,
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PLL_OD_MASK = GENMASK(3, 0),
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/* PLL CON1 */
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PLL_LOCK_STA = BIT(31),
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PLL_NF_SHIFT = 0,
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PLL_NF_MASK = GENMASK(12, 0),
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/* PLL CON2 */
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PLL_BWADJ_SHIFT = 0,
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PLL_BWADJ_MASK = GENMASK(11, 0),
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/* PLL CON3 */
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PLL_MODE_SHIFT = 8,
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PLL_MODE_MASK = GENMASK(9, 8),
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PLL_MODE_SLOW = 0,
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PLL_MODE_NORMAL = 1,
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PLL_MODE_DEEP_SLOW = 3,
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PLL_RESET_SHIFT = 5,
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PLL_RESET = 1,
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PLL_RESET_MASK = GENMASK(5, 5),
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/* CLKSEL1CON */
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CORE_ACLK_DIV_SHIFT = 0,
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CORE_ACLK_DIV_MASK = 0x1f << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0x1f << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
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/* CLKSEL8CON */
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PCLK_BUS_DIV_CON_SHIFT = 12,
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PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT,
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HCLK_BUS_DIV_CON_SHIFT = 8,
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HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT,
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CLK_BUS_PLL_SEL_CPLL = 0,
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CLK_BUS_PLL_SEL_GPLL = 1,
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CLK_BUS_PLL_SEL_SHIFT = 7,
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CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT,
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ACLK_BUS_DIV_CON_SHIFT = 0,
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ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
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/* CLKSEL9CON */
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PCLK_PERI_DIV_CON_SHIFT = 12,
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PCLK_PERI_DIV_CON_MASK = 0x3 << PCLK_PERI_DIV_CON_SHIFT,
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HCLK_PERI_DIV_CON_SHIFT = 8,
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HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT,
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CLK_PERI_PLL_SEL_CPLL = 0,
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CLK_PERI_PLL_SEL_GPLL,
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CLK_PERI_PLL_SEL_SHIFT = 7,
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CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT,
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ACLK_PERI_DIV_CON_SHIFT = 0,
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ACLK_PERI_DIV_CON_MASK = 0x1f,
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/* CLKSEL10CON */
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CLK_CRYPTO_DIV_CON_SHIFT = 14,
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CLK_CRYPTO_DIV_CON_MASK = 0x3 << CLK_CRYPTO_DIV_CON_SHIFT,
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PCLK_ALIVE_DIV_CON_SHIFT = 8,
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PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
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/* CLKSEL12_CON */
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MCU_STCLK_DIV_SHIFT = 8,
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MCU_STCLK_DIV_MASK = GENMASK(10, 8),
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MCU_PLL_SEL_SHIFT = 7,
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MCU_PLL_SEL_MASK = BIT(7),
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MCU_PLL_SEL_CPLL = 0,
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MCU_PLL_SEL_GPLL = 1,
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MCU_CLK_DIV_SHIFT = 0,
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MCU_CLK_DIV_MASK = GENMASK(4, 0),
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/* CLKSEL19_CON */
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ACLK_VOP_PLL_SEL_SHIFT = 6,
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ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6),
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ACLK_VOP_PLL_SEL_CPLL = 0,
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ACLK_VOP_PLL_SEL_GPLL = 1,
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ACLK_VOP_DIV_SHIFT = 0,
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ACLK_VOP_DIV_MASK = GENMASK(4, 0),
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/* CLKSEL20_CON */
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DCLK_VOP_PLL_SEL_SHIFT = 8,
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DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8),
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DCLK_VOP_PLL_SEL_CPLL = 0,
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DCLK_VOP_PLL_SEL_GPLL = 1,
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DCLK_VOP_PLL_SEL_NPLL = 2,
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = GENMASK(7, 0),
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/* CLKSEL_CON25 */
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CLK_SARADC_DIV_CON_SHIFT = 8,
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CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
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CLK_SARADC_DIV_CON_WIDTH = 8,
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/* CLKSEL43_CON */
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GMAC_DIV_CON_SHIFT = 0x0,
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GMAC_DIV_CON_MASK = GENMASK(4, 0),
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GMAC_PLL_SHIFT = 6,
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GMAC_PLL_MASK = GENMASK(7, 6),
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GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
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GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
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GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
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GMAC_MUX_SEL_EXTCLK = BIT(8),
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/* CLKSEL51_CON */
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MMC_PLL_SEL_SHIFT = 8,
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MMC_PLL_SEL_MASK = GENMASK(9, 8),
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MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
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MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
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MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
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MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
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MMC_CLK_DIV_SHIFT = 0,
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MMC_CLK_DIV_MASK = GENMASK(6, 0),
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/* SOFTRST1_CON */
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MCU_PO_SRST_MASK = BIT(13),
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MCU_SYS_SRST_MASK = BIT(12),
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DMA1_SRST_REQ = BIT(2),
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/* SOFTRST4_CON */
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DMA2_SRST_REQ = BIT(0),
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/* GLB_RST_CON */
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PMU_GLB_SRST_CTRL_SHIFT = 2,
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PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
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PMU_RST_BY_FST_GLB_SRST = 0,
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PMU_RST_BY_SND_GLB_SRST = 1,
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PMU_RST_DISABLE = 2,
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WDT_GLB_SRST_CTRL_SHIFT = 1,
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WDT_GLB_SRST_CTRL_MASK = BIT(1),
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WDT_TRIGGER_SND_GLB_SRST = 0,
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WDT_TRIGGER_FST_GLB_SRST = 1,
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TSADC_GLB_SRST_CTRL_SHIFT = 0,
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TSADC_GLB_SRST_CTRL_MASK = BIT(0),
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TSADC_TRIGGER_SND_GLB_SRST = 0,
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TSADC_TRIGGER_FST_GLB_SRST = 1,
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};
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#endif
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