/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK322X_H
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#define _ASM_ARCH_CRU_RK322X_H
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#include <common.h>
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#define MHz 1000 * 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1200 * MHz)
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#define CPLL_HZ (500 * MHz)
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#define ACLK_BUS_HZ (150 * MHz)
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#define ACLK_PERI_HZ (150 * MHz)
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk322x_clk_priv {
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struct rk322x_cru *cru;
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ulong gpll_hz;
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ulong cpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk322x_cru {
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struct rk322x_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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} pll[4];
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unsigned int reserved0[4];
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unsigned int cru_mode_con;
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unsigned int cru_clksel_con[35];
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unsigned int cru_clkgate_con[16];
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unsigned int cru_softrst_con[9];
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unsigned int cru_misc_con;
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unsigned int reserved1[2];
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unsigned int cru_glb_cnt_th;
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unsigned int reserved2[3];
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unsigned int cru_glb_rst_st;
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unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
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unsigned int cru_sdmmc_con[2];
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unsigned int cru_sdio_con[2];
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unsigned int reserved4[2];
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unsigned int cru_emmc_con[2];
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unsigned int reserved5[4];
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unsigned int cru_glb_srst_fst_value;
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unsigned int cru_glb_srst_snd_value;
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unsigned int cru_pll_mask_con;
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};
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check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
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enum rk322x_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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NPLL,
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PLL_COUNT,
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};
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struct rk322x_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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#define RK2928_PLL_CON(x) ((x) * 0x4)
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#define RK2928_MODE_CON 0x40
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enum {
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/* CRU_CLK_SEL0_CON */
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BUS_ACLK_PLL_SEL_SHIFT = 13,
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BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
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BUS_ACLK_PLL_SEL_CPLL = 0,
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BUS_ACLK_PLL_SEL_GPLL,
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BUS_ACLK_PLL_SEL_HDMIPLL,
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BUS_ACLK_DIV_SHIFT = 8,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 6,
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CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_CLK_PLL_SEL_DPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL1_CON */
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BUS_PCLK_DIV_SHIFT = 12,
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BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 8,
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BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
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CORE_PERI_DIV_SHIFT = 0,
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CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
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/* CRU_CLKSEL5_CON */
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GMAC_OUT_PLL_SHIFT = 15,
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GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
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GMAC_OUT_DIV_SHIFT = 8,
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GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
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MAC_PLL_SEL_SHIFT = 7,
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MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
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RMII_EXTCLK_SLE_SHIFT = 5,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
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RMII_EXTCLK_SEL_INT = 0,
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RMII_EXTCLK_SEL_EXT,
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CLK_MAC_DIV_SHIFT = 0,
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CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
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/* CRU_CLKSEL10_CON */
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PERI_PCLK_DIV_SHIFT = 12,
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PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
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PERI_PLL_SEL_SHIFT = 10,
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PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_CPLL = 0,
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PERI_PLL_GPLL,
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PERI_PLL_HDMIPLL,
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLKSEL11_CON */
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EMMC_PLL_SHIFT = 12,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_CPLL = 0,
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EMMC_SEL_GPLL,
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EMMC_SEL_24M,
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SDIO_PLL_SHIFT = 10,
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SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
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SDIO_SEL_CPLL = 0,
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SDIO_SEL_GPLL,
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SDIO_SEL_24M,
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MMC0_PLL_SHIFT = 8,
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MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
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MMC0_SEL_CPLL = 0,
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MMC0_SEL_GPLL,
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MMC0_SEL_24M,
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
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/* CRU_CLKSEL12_CON */
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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SDIO_DIV_SHIFT = 0,
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SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
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/* CLKSEL_CON24 */
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CRYPTO_PLL_SEL_SHIFT = 5,
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CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_PLL_SEL_CPLL = 0,
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CRYPTO_PLL_SEL_GPLL,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CLKSEL_CON25 */
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SPI_PLL_SEL_SHIFT = 8,
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SPI_PLL_SEL_MASK = 0x1 << SPI_PLL_SEL_SHIFT,
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SPI_PLL_SEL_CPLL = 0,
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SPI_PLL_SEL_GPLL,
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SPI_DIV_SHIFT = 0,
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SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT,
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/* CRU_CLKSEL26_CON */
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DDR_CLK_PLL_SEL_SHIFT = 8,
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DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
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DDR_CLK_SEL_DPLL = 0,
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DDR_CLK_SEL_GPLL,
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DDR_CLK_SEL_APLL,
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DDR_DIV_SEL_SHIFT = 0,
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DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
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/* CRU_CLKSEL27_CON */
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DCLK_LCDC_PLL_SEL_GPLL = 0,
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DCLK_LCDC_PLL_SEL_CPLL = 1,
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DCLK_LCDC_PLL_SEL_SHIFT = 0,
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DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
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DCLK_LCDC_SEL_HDMIPHY = 0,
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DCLK_LCDC_SEL_PLL = 1,
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DCLK_LCDC_SEL_SHIFT = 1,
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DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
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DCLK_LCDC_DIV_CON_SHIFT = 8,
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DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
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/* CRU_CLKSEL29_CON */
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GMAC_CLK_SRC_SHIFT = 12,
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GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
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/* CRU_CLKSEL33_CON */
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ACLK_VOP_PLL_SEL_SHIFT = 5,
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ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
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ACLK_VOP_PLL_SEL_CPLL = 0,
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ACLK_VOP_PLL_SEL_GPLL = 1,
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ACLK_VOP_PLL_SEL_HDMIPHY = 2,
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ACLK_VOP_DIV_CON_SHIFT = 0,
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ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
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/* CRU_SOFTRST5_CON */
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DDRCTRL_PSRST_SHIFT = 11,
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DDRCTRL_SRST_SHIFT = 10,
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DDRPHY_PSRST_SHIFT = 9,
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DDRPHY_SRST_SHIFT = 8,
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};
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#endif
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