/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_CRU_rk1808_H
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#define _ASM_ARCH_CRU_rk1808_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (1200 * MHz)
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#define PCLK_PMU_HZ (100 * MHz)
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#define GPLL_HZ (594 * MHz)
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/* PX30 pll id */
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enum rk1808_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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NPLL,
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PPLL,
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PLL_COUNT,
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};
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struct rk1808_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk1808_clk_priv {
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struct rk1808_cru *cru;
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ulong armclk_hz;
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ulong cpll_hz;
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ulong gpll_hz;
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ulong npll_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk1808_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct rk1808_cru {
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struct rk1808_pll pll[5];
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unsigned int mode;
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unsigned int misc;
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unsigned int misc1;
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unsigned int reserved2[1];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved3[7];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[73];
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unsigned int reserved6[3];
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unsigned int clkgate_con[20];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[16];
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unsigned int reserved7[(0x380 - 0x33c) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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unsigned int reserved8[(0x400 - 0x394) / 4 - 1];
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unsigned int autocs_con[10];
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unsigned int reserved9[(0x4000 - 0x424) / 4 - 1];
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struct rk1808_pll pmu_pll;
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unsigned int pmu_mode;
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unsigned int reserved10[(0x4040 - 0x4020) / 4 - 1];
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unsigned int pmu_clksel_con[8];
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unsigned int reserved11[(0x4080 - 0x405c) / 4 - 1];
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unsigned int pmu_clkgate_con[2];
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unsigned int reserved12[(0x40c0 - 0x4084) / 4 - 1];
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unsigned int pmu_autocs_con[2];
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};
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check_member(rk1808_cru, pmu_autocs_con[0], 0x40c0);
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#define RK1808_PLL_CON(x) ((x) * 0x4)
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#define RK1808_MODE_CON 0xa0
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#define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
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#define RK1808_PMU_MODE_CON 0x4020
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enum {
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/* CRU_CLK_SEL0_CON */
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CORE_ACLK_DIV_SHIFT = 12,
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CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL4_CON */
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ACLK_VOP_PLL_SEL_GPLL = 0,
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ACLK_VOP_PLL_SEL_CPLL = 1,
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ACLK_VOP_PLL_SEL_SHIFT = 7,
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ACLK_VOP_PLL_SEL_MASK = 1 << ACLK_VOP_PLL_SEL_SHIFT,
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ACLK_VOP_DIV_CON_SHIFT = 0,
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ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
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HCLK_VOP_DIV_CON_SHIFT = 8,
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HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT,
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/* CRU_CLK_SEL5_CON */
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DCLK_VOPRAW_SEL_VOPRAW = 0,
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DCLK_VOPRAW_SEL_VOPRAW_FRAC = 1,
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DCLK_VOPRAW_SEL_XIN24M = 2,
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DCLK_VOPRAW_SEL_SHIFT = 14,
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DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT,
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DCLK_VOPRAW_PLL_SEL_CPLL = 0,
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DCLK_VOPRAW_PLL_SEL_GPLL = 1,
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DCLK_VOPRAW_PLL_SEL_NPLL = 2,
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DCLK_VOPRAW_PLL_SEL_SHIFT = 10,
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DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT,
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DCLK_VOPRAW_DIV_CON_SHIFT = 0,
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DCLK_VOPRAW_DIV_CON_MASK = 0xff << DCLK_VOPRAW_DIV_CON_SHIFT,
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/* CRU_CLK_SEL7_CON */
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DCLK_VOPLITE_SEL_VOPRAW = 0,
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DCLK_VOPLITE_SEL_VOPRAW_FRAC = 1,
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DCLK_VOPLITE_SEL_XIN24M = 2,
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DCLK_VOPLITE_SEL_SHIFT = 14,
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DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT,
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DCLK_VOPLITE_PLL_SEL_CPLL = 0,
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DCLK_VOPLITE_PLL_SEL_GPLL = 1,
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DCLK_VOPLITE_PLL_SEL_NPLL = 2,
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DCLK_VOPLITE_PLL_SEL_SHIFT = 10,
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DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT,
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DCLK_VOPLITE_DIV_CON_SHIFT = 0,
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DCLK_VOPLITE_DIV_CON_MASK = 0xff << DCLK_VOPLITE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL19_CON */
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CLK_PERI_PLL_SEL_GPLL = 0,
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CLK_PERI_PLL_SEL_CPLL = 1,
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CLK_PERI_PLL_SEL_SHIFT = 15,
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CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT,
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LSCLK_PERI_DIV_CON_SHIFT = 8,
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LSCLK_PERI_DIV_CON_MASK = 0x1f << LSCLK_PERI_DIV_CON_SHIFT,
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MSCLK_PERI_DIV_CON_SHIFT = 0,
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MSCLK_PERI_DIV_CON_MASK = 0x1f << MSCLK_PERI_DIV_CON_SHIFT,
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/* CRU_CLKSEL24_CON */
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EMMC_PLL_SHIFT = 14,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_GPLL = 0,
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EMMC_SEL_CPLL,
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EMMC_SEL_NPLL,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL25_CON */
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EMMC_CLK_SEL_SHIFT = 15,
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EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
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EMMC_CLK_SEL_EMMC = 0,
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EMMC_CLK_SEL_EMMC_DIV50,
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EMMC_DIV50_SHIFT = 0,
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EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL26_CON */
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GMAC_PLL_SEL_SHIFT = 14,
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GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
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GMAC_PLL_SEL_CPLL = 0,
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GMAC_PLL_SEL_NPLL,
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GMAC_PLL_SEL_PPLL,
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CLK_GMAC_DIV_SHIFT = 8,
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CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
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SFC_PLL_SEL_SHIFT = 7,
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
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SFC_DIV_CON_SHIFT = 0,
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SFC_DIV_CON_MASK = 0x7f,
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/* CRU_CLK_SEL27_CON */
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CLK_BUS_PLL_SEL_GPLL = 0,
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CLK_BUS_PLL_SEL_CPLL = 1,
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CLK_BUS_PLL_SEL_SHIFT = 15,
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CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT,
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HSCLK_BUS_DIV_CON_SHIFT = 8,
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HSCLK_BUS_DIV_CON_MASK = 0x1f << HSCLK_BUS_DIV_CON_SHIFT,
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RGMII_CLK_SEL_SHIFT = 2,
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RGMII_CLK_SEL_MASK = 3 << RGMII_CLK_SEL_SHIFT,
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RGMII_CLK_SEL_125M = 0,
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RGMII_CLK_SEL_2M = 2,
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RGMIIC_CLK_SEL_25M = 3,
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RMII_CLK_SEL_SHIFT = 1,
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RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
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RMII_EXTCLK_SEL_SHIFT = 0,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
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RMII_EXTCLK_SEL_INT = 0,
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RMII_EXTCLK_SEL_EXT,
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/* CRU_CLK_SEL28_CON */
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MSCLK_BUS_DIV_CON_SHIFT = 8,
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MSCLK_BUS_DIV_CON_MASK = 0x1f << MSCLK_BUS_DIV_CON_SHIFT,
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LSCLK_BUS_DIV_CON_SHIFT = 0,
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LSCLK_BUS_DIV_CON_MASK = 0x1f << LSCLK_BUS_DIV_CON_SHIFT,
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/* CRU_CLK_SEL29_CON */
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CRYPTO_APK_SEL_SHIFT = 15,
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CRYPTO_APK_PLL_SEL_MASK = 1 << CRYPTO_APK_SEL_SHIFT,
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CRYPTO_PLL_SEL_GPLL = 0,
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CRYPTO_PLL_SEL_CPLL,
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CRYPTO_APK_DIV_SHIFT = 8,
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CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
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CRYPTO_PLL_SEL_SHIFT = 7,
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CRYPTO_PLL_SEL_MASK = 1 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CRU_CLK_SEL59_CON */
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CLK_I2C_PLL_SEL_GPLL = 0,
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CLK_I2C_PLL_SEL_24M,
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CLK_I2C2_PLL_SEL_SHIFT = 15,
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CLK_I2C2_DIV_CON_SHIFT = 8,
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CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT,
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CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT,
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CLK_I2C1_PLL_SEL_SHIFT = 7,
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CLK_I2C1_DIV_CON_SHIFT = 0,
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CLK_I2C1_DIV_CON_MASK = 0x7f,
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CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT,
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/* CRU_CLK_SEL60_CON */
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CLK_SPI_PLL_SEL_GPLL = 0,
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CLK_SPI_PLL_SEL_24M,
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CLK_SPI0_PLL_SEL_SHIFT = 15,
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CLK_SPI0_DIV_CON_SHIFT = 8,
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CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT,
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CLK_SPI0_PLL_SEL_MASK = 1 << CLK_SPI0_PLL_SEL_SHIFT,
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CLK_I2C3_PLL_SEL_SHIFT = 7,
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CLK_I2C3_DIV_CON_SHIFT = 0,
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CLK_I2C3_DIV_CON_MASK = 0x7f,
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CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT,
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/* CRU_CLK_SEL61_CON */
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CLK_SPI2_PLL_SEL_SHIFT = 15,
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CLK_SPI2_DIV_CON_SHIFT = 8,
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CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT,
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CLK_SPI2_PLL_SEL_MASK = 1 << CLK_SPI2_PLL_SEL_SHIFT,
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CLK_SPI1_PLL_SEL_SHIFT = 7,
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CLK_SPI1_DIV_CON_SHIFT = 0,
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CLK_SPI1_DIV_CON_MASK = 0x7f,
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CLK_SPI1_PLL_SEL_MASK = 1 << CLK_SPI1_PLL_SEL_SHIFT,
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/* CRU_CLK_SEL62_CON */
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CLK_TSADC_DIV_CON_SHIFT = 0,
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CLK_TSADC_DIV_CON_MASK = 0x3ff,
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/* CRU_CLK_SEL63_CON */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = 0x3ff,
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/* CRU_CLK_SEL69_CON */
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CLK_PWM_PLL_SEL_GPLL = 0,
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CLK_PWM_PLL_SEL_24M,
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CLK_PWM1_PLL_SEL_SHIFT = 15,
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CLK_PWM1_DIV_CON_SHIFT = 8,
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CLK_PWM1_DIV_CON_MASK = 0x7f << CLK_PWM1_DIV_CON_SHIFT,
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CLK_PWM1_PLL_SEL_MASK = 1 << CLK_PWM1_PLL_SEL_SHIFT,
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CLK_PWM0_PLL_SEL_SHIFT = 7,
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CLK_PWM0_DIV_CON_SHIFT = 0,
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CLK_PWM0_DIV_CON_MASK = 0x7f,
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CLK_PWM0_PLL_SEL_MASK = 1 << CLK_PWM0_PLL_SEL_SHIFT,
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/* CRU_CLK_SEL70_CON */
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CLK_PWM2_PLL_SEL_SHIFT = 7,
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CLK_PWM2_DIV_CON_SHIFT = 0,
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CLK_PWM2_DIV_CON_MASK = 0x7f,
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CLK_PWM2_PLL_SEL_MASK = 1 << CLK_PWM2_PLL_SEL_SHIFT,
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/* CRU_CLK_SEL71_CON */
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CLK_I2C5_PLL_SEL_SHIFT = 15,
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CLK_I2C5_DIV_CON_SHIFT = 8,
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CLK_I2C5_DIV_CON_MASK = 0x7f << CLK_I2C5_DIV_CON_SHIFT,
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CLK_I2C5_PLL_SEL_MASK = 1 << CLK_I2C5_PLL_SEL_SHIFT,
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CLK_I2C4_PLL_SEL_SHIFT = 7,
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CLK_I2C4_DIV_CON_SHIFT = 0,
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CLK_I2C4_DIV_CON_MASK = 0x7f,
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CLK_I2C4_PLL_SEL_MASK = 1 << CLK_I2C4_PLL_SEL_SHIFT,
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/* CRU_PMU_CLK_SEL7_CON */
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CLK_I2C0_PLL_SEL_PPLL = 0,
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CLK_I2C0_PLL_SEL_SHIFT = 15,
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CLK_I2C0_DIV_CON_SHIFT = 8,
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CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT,
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CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT,
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/* PMUCRU_CLK_SEL0_CON */
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PCLK_PMU_DIV_CON_SHIFT = 0,
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PCLK_PMU_DIV_CON_MASK = 0x1f << PCLK_PMU_DIV_CON_SHIFT,
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};
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#endif
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