/*
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* (C) Copyright 2014
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/stv0991_cgu.h>
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#include<asm/arch/stv0991_periph.h>
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static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
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(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
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void enable_pll1(void)
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{
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/* pll1 already configured for 1000Mhz, just need to enable it */
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writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
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&stv0991_cgu_regs->pll1_ctrl);
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}
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void clock_setup(int peripheral)
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{
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switch (peripheral) {
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case UART_CLOCK_CFG:
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writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
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break;
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case ETH_CLOCK_CFG:
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enable_pll1();
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writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
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/* Clock selection for ethernet tx_clk & rx_clk*/
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writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
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| ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
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break;
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case QSPI_CLOCK_CFG:
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writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
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break;
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default:
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break;
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}
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}
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