/*
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* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <linux/types.h>
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#include <asm/arch/sys_proto.h>
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#define ESDCTL_DDR2_EMR2 0x04000000
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#define ESDCTL_DDR2_EMR3 0x06000000
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#define ESDCTL_PRECHARGE 0x00000400
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#define ESDCTL_DDR2_EN_DLL 0x02000400
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#define ESDCTL_DDR2_RESET_DLL 0x00000333
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#define ESDCTL_DDR2_MR 0x00000233
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#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
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enum {
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SMODE_NORMAL = 0,
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SMODE_PRECHARGE,
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SMODE_AUTO_REFRESH,
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SMODE_LOAD_REG,
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SMODE_MANUAL_REFRESH
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};
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#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
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static inline void dram_wait(unsigned int count)
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{
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volatile unsigned int wait = count;
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while (wait--)
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;
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}
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void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
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u32 row, u32 col, u32 dsize, u32 refresh)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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u32 *cfg_reg, *ctl_reg;
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u32 val;
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u32 ctlval;
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switch (start_address) {
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case CSD0_BASE_ADDR:
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cfg_reg = &esdc->esdcfg0;
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ctl_reg = &esdc->esdctl0;
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break;
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case CSD1_BASE_ADDR:
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cfg_reg = &esdc->esdcfg1;
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ctl_reg = &esdc->esdctl1;
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break;
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default:
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return;
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}
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/* The MX35 supports 11 up to 14 rows */
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if (row < 11 || row > 14 || col < 8 || col > 10)
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return;
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ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
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/* Initialize MISC register for DDR2 */
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val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
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ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
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writel(val, &esdc->esdmisc);
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val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
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writel(val, &esdc->esdmisc);
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/*
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* according to DDR2 specs, wait a while before
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* the PRECHARGE_ALL command
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*/
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dram_wait(0x20000);
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/* Load DDR2 config and timing */
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writel(ddr2_config, cfg_reg);
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/* Precharge ALL */
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writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Load mode */
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writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
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writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
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/* Precharge ALL */
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writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Set mode auto refresh : at least two refresh are required */
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writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
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ctl_reg);
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writel(0xda, start_address);
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writel(0xda, start_address);
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writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_MR);
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writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
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/* OCD mode exit */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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/* Set normal mode */
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writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
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ctl_reg);
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dram_wait(0x20000);
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/* Do not set delay lines, only for MDDR */
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}
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