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<title>Using the GNU Compiler Collection (GCC): DEC Alpha Options</title>
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<a name="DEC-Alpha-Options"></a>
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<p>
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Next: <a href="FR30-Options.html#FR30-Options" accesskey="n" rel="next">FR30 Options</a>, Previous: <a href="Darwin-Options.html#Darwin-Options" accesskey="p" rel="prev">Darwin Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="DEC-Alpha-Options-1"></a>
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<h4 class="subsection">3.18.11 DEC Alpha Options</h4>
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<p>These ‘<samp>-m</samp>’ options are defined for the DEC Alpha implementations:
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</p>
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<dl compact="compact">
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<dt><code>-mno-soft-float</code></dt>
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<dt><code>-msoft-float</code></dt>
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<dd><a name="index-mno_002dsoft_002dfloat"></a>
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<a name="index-msoft_002dfloat-1"></a>
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<p>Use (do not use) the hardware floating-point instructions for
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floating-point operations. When <samp>-msoft-float</samp> is specified,
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functions in <samp>libgcc.a</samp> are used to perform floating-point
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operations. Unless they are replaced by routines that emulate the
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floating-point operations, or compiled in such a way as to call such
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emulations routines, these routines issue floating-point
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operations. If you are compiling for an Alpha without floating-point
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operations, you must ensure that the library is built so as not to call
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them.
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</p>
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<p>Note that Alpha implementations without floating-point operations are
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required to have floating-point registers.
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</p>
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</dd>
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<dt><code>-mfp-reg</code></dt>
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<dt><code>-mno-fp-regs</code></dt>
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<dd><a name="index-mfp_002dreg"></a>
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<a name="index-mno_002dfp_002dregs"></a>
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<p>Generate code that uses (does not use) the floating-point register set.
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<samp>-mno-fp-regs</samp> implies <samp>-msoft-float</samp>. If the floating-point
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register set is not used, floating-point operands are passed in integer
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registers as if they were integers and floating-point results are passed
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in <code>$0</code> instead of <code>$f0</code>. This is a non-standard calling sequence,
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so any function with a floating-point argument or return value called by code
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compiled with <samp>-mno-fp-regs</samp> must also be compiled with that
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option.
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</p>
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<p>A typical use of this option is building a kernel that does not use,
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and hence need not save and restore, any floating-point registers.
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</p>
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</dd>
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<dt><code>-mieee</code></dt>
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<dd><a name="index-mieee"></a>
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<p>The Alpha architecture implements floating-point hardware optimized for
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maximum performance. It is mostly compliant with the IEEE floating-point
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standard. However, for full compliance, software assistance is
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required. This option generates code fully IEEE-compliant code
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<em>except</em> that the <var>inexact-flag</var> is not maintained (see below).
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If this option is turned on, the preprocessor macro <code>_IEEE_FP</code> is
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defined during compilation. The resulting code is less efficient but is
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able to correctly support denormalized numbers and exceptional IEEE
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values such as not-a-number and plus/minus infinity. Other Alpha
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compilers call this option <samp>-ieee_with_no_inexact</samp>.
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</p>
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</dd>
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<dt><code>-mieee-with-inexact</code></dt>
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<dd><a name="index-mieee_002dwith_002dinexact"></a>
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<p>This is like <samp>-mieee</samp> except the generated code also maintains
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the IEEE <var>inexact-flag</var>. Turning on this option causes the
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generated code to implement fully-compliant IEEE math. In addition to
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<code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessor
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macro. On some Alpha implementations the resulting code may execute
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significantly slower than the code generated by default. Since there is
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very little code that depends on the <var>inexact-flag</var>, you should
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normally not specify this option. Other Alpha compilers call this
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option <samp>-ieee_with_inexact</samp>.
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</p>
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</dd>
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<dt><code>-mfp-trap-mode=<var>trap-mode</var></code></dt>
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<dd><a name="index-mfp_002dtrap_002dmode"></a>
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<p>This option controls what floating-point related traps are enabled.
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Other Alpha compilers call this option <samp>-fptm <var>trap-mode</var></samp>.
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The trap mode can be set to one of four values:
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</p>
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<dl compact="compact">
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<dt>‘<samp>n</samp>’</dt>
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<dd><p>This is the default (normal) setting. The only traps that are enabled
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are the ones that cannot be disabled in software (e.g., division by zero
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trap).
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</p>
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</dd>
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<dt>‘<samp>u</samp>’</dt>
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<dd><p>In addition to the traps enabled by ‘<samp>n</samp>’, underflow traps are enabled
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as well.
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</p>
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</dd>
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<dt>‘<samp>su</samp>’</dt>
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<dd><p>Like ‘<samp>u</samp>’, but the instructions are marked to be safe for software
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completion (see Alpha architecture manual for details).
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</p>
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</dd>
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<dt>‘<samp>sui</samp>’</dt>
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<dd><p>Like ‘<samp>su</samp>’, but inexact traps are enabled as well.
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</p></dd>
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</dl>
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</dd>
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<dt><code>-mfp-rounding-mode=<var>rounding-mode</var></code></dt>
|
<dd><a name="index-mfp_002drounding_002dmode"></a>
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<p>Selects the IEEE rounding mode. Other Alpha compilers call this option
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<samp>-fprm <var>rounding-mode</var></samp>. The <var>rounding-mode</var> can be one
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of:
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</p>
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<dl compact="compact">
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<dt>‘<samp>n</samp>’</dt>
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<dd><p>Normal IEEE rounding mode. Floating-point numbers are rounded towards
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the nearest machine number or towards the even machine number in case
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of a tie.
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</p>
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</dd>
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<dt>‘<samp>m</samp>’</dt>
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<dd><p>Round towards minus infinity.
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</p>
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</dd>
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<dt>‘<samp>c</samp>’</dt>
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<dd><p>Chopped rounding mode. Floating-point numbers are rounded towards zero.
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</p>
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</dd>
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<dt>‘<samp>d</samp>’</dt>
|
<dd><p>Dynamic rounding mode. A field in the floating-point control register
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(<var>fpcr</var>, see Alpha architecture reference manual) controls the
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rounding mode in effect. The C library initializes this register for
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rounding towards plus infinity. Thus, unless your program modifies the
|
<var>fpcr</var>, ‘<samp>d</samp>’ corresponds to round towards plus infinity.
|
</p></dd>
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</dl>
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</dd>
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<dt><code>-mtrap-precision=<var>trap-precision</var></code></dt>
|
<dd><a name="index-mtrap_002dprecision"></a>
|
<p>In the Alpha architecture, floating-point traps are imprecise. This
|
means without software assistance it is impossible to recover from a
|
floating trap and program execution normally needs to be terminated.
|
GCC can generate code that can assist operating system trap handlers
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in determining the exact location that caused a floating-point trap.
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Depending on the requirements of an application, different levels of
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precisions can be selected:
|
</p>
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<dl compact="compact">
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<dt>‘<samp>p</samp>’</dt>
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<dd><p>Program precision. This option is the default and means a trap handler
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can only identify which program caused a floating-point exception.
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</p>
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</dd>
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<dt>‘<samp>f</samp>’</dt>
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<dd><p>Function precision. The trap handler can determine the function that
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caused a floating-point exception.
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</p>
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</dd>
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<dt>‘<samp>i</samp>’</dt>
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<dd><p>Instruction precision. The trap handler can determine the exact
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instruction that caused a floating-point exception.
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</p></dd>
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</dl>
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<p>Other Alpha compilers provide the equivalent options called
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<samp>-scope_safe</samp> and <samp>-resumption_safe</samp>.
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</p>
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</dd>
|
<dt><code>-mieee-conformant</code></dt>
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<dd><a name="index-mieee_002dconformant"></a>
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<p>This option marks the generated code as IEEE conformant. You must not
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use this option unless you also specify <samp>-mtrap-precision=i</samp> and either
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<samp>-mfp-trap-mode=su</samp> or <samp>-mfp-trap-mode=sui</samp>. Its only effect
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is to emit the line ‘<samp>.eflag 48</samp>’ in the function prologue of the
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generated assembly file.
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</p>
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</dd>
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<dt><code>-mbuild-constants</code></dt>
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<dd><a name="index-mbuild_002dconstants"></a>
|
<p>Normally GCC examines a 32- or 64-bit integer constant to
|
see if it can construct it from smaller constants in two or three
|
instructions. If it cannot, it outputs the constant as a literal and
|
generates code to load it from the data segment at run time.
|
</p>
|
<p>Use this option to require GCC to construct <em>all</em> integer constants
|
using code, even if it takes more instructions (the maximum is six).
|
</p>
|
<p>You typically use this option to build a shared library dynamic
|
loader. Itself a shared library, it must relocate itself in memory
|
before it can find the variables and constants in its own data segment.
|
</p>
|
</dd>
|
<dt><code>-mbwx</code></dt>
|
<dt><code>-mno-bwx</code></dt>
|
<dt><code>-mcix</code></dt>
|
<dt><code>-mno-cix</code></dt>
|
<dt><code>-mfix</code></dt>
|
<dt><code>-mno-fix</code></dt>
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<dt><code>-mmax</code></dt>
|
<dt><code>-mno-max</code></dt>
|
<dd><a name="index-mbwx"></a>
|
<a name="index-mno_002dbwx"></a>
|
<a name="index-mcix"></a>
|
<a name="index-mno_002dcix"></a>
|
<a name="index-mfix"></a>
|
<a name="index-mno_002dfix"></a>
|
<a name="index-mmax"></a>
|
<a name="index-mno_002dmax"></a>
|
<p>Indicate whether GCC should generate code to use the optional BWX,
|
CIX, FIX and MAX instruction sets. The default is to use the instruction
|
sets supported by the CPU type specified via <samp>-mcpu=</samp> option or that
|
of the CPU on which GCC was built if none is specified.
|
</p>
|
</dd>
|
<dt><code>-mfloat-vax</code></dt>
|
<dt><code>-mfloat-ieee</code></dt>
|
<dd><a name="index-mfloat_002dvax"></a>
|
<a name="index-mfloat_002dieee"></a>
|
<p>Generate code that uses (does not use) VAX F and G floating-point
|
arithmetic instead of IEEE single and double precision.
|
</p>
|
</dd>
|
<dt><code>-mexplicit-relocs</code></dt>
|
<dt><code>-mno-explicit-relocs</code></dt>
|
<dd><a name="index-mexplicit_002drelocs"></a>
|
<a name="index-mno_002dexplicit_002drelocs"></a>
|
<p>Older Alpha assemblers provided no way to generate symbol relocations
|
except via assembler macros. Use of these macros does not allow
|
optimal instruction scheduling. GNU binutils as of version 2.12
|
supports a new syntax that allows the compiler to explicitly mark
|
which relocations should apply to which instructions. This option
|
is mostly useful for debugging, as GCC detects the capabilities of
|
the assembler when it is built and sets the default accordingly.
|
</p>
|
</dd>
|
<dt><code>-msmall-data</code></dt>
|
<dt><code>-mlarge-data</code></dt>
|
<dd><a name="index-msmall_002ddata"></a>
|
<a name="index-mlarge_002ddata"></a>
|
<p>When <samp>-mexplicit-relocs</samp> is in effect, static data is
|
accessed via <em>gp-relative</em> relocations. When <samp>-msmall-data</samp>
|
is used, objects 8 bytes long or smaller are placed in a <em>small data area</em>
|
(the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via
|
16-bit relocations off of the <code>$gp</code> register. This limits the
|
size of the small data area to 64KB, but allows the variables to be
|
directly accessed via a single instruction.
|
</p>
|
<p>The default is <samp>-mlarge-data</samp>. With this option the data area
|
is limited to just below 2GB. Programs that require more than 2GB of
|
data must use <code>malloc</code> or <code>mmap</code> to allocate the data in the
|
heap instead of in the program’s data segment.
|
</p>
|
<p>When generating code for shared libraries, <samp>-fpic</samp> implies
|
<samp>-msmall-data</samp> and <samp>-fPIC</samp> implies <samp>-mlarge-data</samp>.
|
</p>
|
</dd>
|
<dt><code>-msmall-text</code></dt>
|
<dt><code>-mlarge-text</code></dt>
|
<dd><a name="index-msmall_002dtext"></a>
|
<a name="index-mlarge_002dtext"></a>
|
<p>When <samp>-msmall-text</samp> is used, the compiler assumes that the
|
code of the entire program (or shared library) fits in 4MB, and is
|
thus reachable with a branch instruction. When <samp>-msmall-data</samp>
|
is used, the compiler can assume that all local symbols share the
|
same <code>$gp</code> value, and thus reduce the number of instructions
|
required for a function call from 4 to 1.
|
</p>
|
<p>The default is <samp>-mlarge-text</samp>.
|
</p>
|
</dd>
|
<dt><code>-mcpu=<var>cpu_type</var></code></dt>
|
<dd><a name="index-mcpu-4"></a>
|
<p>Set the instruction set and instruction scheduling parameters for
|
machine type <var>cpu_type</var>. You can specify either the ‘<samp>EV</samp>’
|
style name or the corresponding chip number. GCC supports scheduling
|
parameters for the EV4, EV5 and EV6 family of processors and
|
chooses the default values for the instruction set from the processor
|
you specify. If you do not specify a processor type, GCC defaults
|
to the processor on which the compiler was built.
|
</p>
|
<p>Supported values for <var>cpu_type</var> are
|
</p>
|
<dl compact="compact">
|
<dt>‘<samp>ev4</samp>’</dt>
|
<dt>‘<samp>ev45</samp>’</dt>
|
<dt>‘<samp>21064</samp>’</dt>
|
<dd><p>Schedules as an EV4 and has no instruction set extensions.
|
</p>
|
</dd>
|
<dt>‘<samp>ev5</samp>’</dt>
|
<dt>‘<samp>21164</samp>’</dt>
|
<dd><p>Schedules as an EV5 and has no instruction set extensions.
|
</p>
|
</dd>
|
<dt>‘<samp>ev56</samp>’</dt>
|
<dt>‘<samp>21164a</samp>’</dt>
|
<dd><p>Schedules as an EV5 and supports the BWX extension.
|
</p>
|
</dd>
|
<dt>‘<samp>pca56</samp>’</dt>
|
<dt>‘<samp>21164pc</samp>’</dt>
|
<dt>‘<samp>21164PC</samp>’</dt>
|
<dd><p>Schedules as an EV5 and supports the BWX and MAX extensions.
|
</p>
|
</dd>
|
<dt>‘<samp>ev6</samp>’</dt>
|
<dt>‘<samp>21264</samp>’</dt>
|
<dd><p>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
|
</p>
|
</dd>
|
<dt>‘<samp>ev67</samp>’</dt>
|
<dt>‘<samp>21264a</samp>’</dt>
|
<dd><p>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
|
</p></dd>
|
</dl>
|
|
<p>Native toolchains also support the value ‘<samp>native</samp>’,
|
which selects the best architecture option for the host processor.
|
<samp>-mcpu=native</samp> has no effect if GCC does not recognize
|
the processor.
|
</p>
|
</dd>
|
<dt><code>-mtune=<var>cpu_type</var></code></dt>
|
<dd><a name="index-mtune-5"></a>
|
<p>Set only the instruction scheduling parameters for machine type
|
<var>cpu_type</var>. The instruction set is not changed.
|
</p>
|
<p>Native toolchains also support the value ‘<samp>native</samp>’,
|
which selects the best architecture option for the host processor.
|
<samp>-mtune=native</samp> has no effect if GCC does not recognize
|
the processor.
|
</p>
|
</dd>
|
<dt><code>-mmemory-latency=<var>time</var></code></dt>
|
<dd><a name="index-mmemory_002dlatency"></a>
|
<p>Sets the latency the scheduler should assume for typical memory
|
references as seen by the application. This number is highly
|
dependent on the memory access patterns used by the application
|
and the size of the external cache on the machine.
|
</p>
|
<p>Valid options for <var>time</var> are
|
</p>
|
<dl compact="compact">
|
<dt>‘<samp><var>number</var></samp>’</dt>
|
<dd><p>A decimal number representing clock cycles.
|
</p>
|
</dd>
|
<dt>‘<samp>L1</samp>’</dt>
|
<dt>‘<samp>L2</samp>’</dt>
|
<dt>‘<samp>L3</samp>’</dt>
|
<dt>‘<samp>main</samp>’</dt>
|
<dd><p>The compiler contains estimates of the number of clock cycles for
|
“typical” EV4 & EV5 hardware for the Level 1, 2 & 3 caches
|
(also called Dcache, Scache, and Bcache), as well as to main memory.
|
Note that L3 is only valid for EV5.
|
</p>
|
</dd>
|
</dl>
|
</dd>
|
</dl>
|
|
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|
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<p>
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Next: <a href="FR30-Options.html#FR30-Options" accesskey="n" rel="next">FR30 Options</a>, Previous: <a href="Darwin-Options.html#Darwin-Options" accesskey="p" rel="prev">Darwin Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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