/******************************************************************************
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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*****************************************************************************/
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#ifndef R8180_HW
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#define R8180_HW
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enum baseband_config {
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BaseBand_Config_PHY_REG = 0,
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BaseBand_Config_AGC_TAB = 1,
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};
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#define RTL8187_REQT_READ 0xc0
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#define RTL8187_REQT_WRITE 0x40
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#define RTL8187_REQ_GET_REGS 0x05
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#define RTL8187_REQ_SET_REGS 0x05
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#define MAX_TX_URB 5
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#define MAX_RX_URB 16
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#define RX_URB_SIZE 9100
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#define BB_ANTATTEN_CHAN14 0x0c
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#define BB_ANTENNA_B 0x40
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#define BB_HOST_BANG (1<<30)
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#define BB_HOST_BANG_EN (1<<2)
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#define BB_HOST_BANG_CLK (1<<1)
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#define BB_HOST_BANG_RW (1<<3)
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#define BB_HOST_BANG_DATA 1
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#define RTL8190_EEPROM_ID 0x8129
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#define EEPROM_VID 0x02
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#define EEPROM_DID 0x04
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#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
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#define EEPROM_TxPowerDiff 0x1F
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#define EEPROM_PwDiff 0x21
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#define EEPROM_CrystalCap 0x22
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#define EEPROM_TxPwIndex_CCK_V1 0x29
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#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C
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#define EEPROM_TxPwIndex_Ver 0x27
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#define EEPROM_Default_TxPowerDiff 0x0
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#define EEPROM_Default_ThermalMeter 0x77
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#define EEPROM_Default_AntTxPowerDiff 0x0
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#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
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#define EEPROM_Default_PwDiff 0x4
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#define EEPROM_Default_CrystalCap 0x5
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#define EEPROM_Default_TxPower 0x1010
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#define EEPROM_ICVersion_ChannelPlan 0x7C
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#define EEPROM_Customer_ID 0x7B
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#define EEPROM_RFInd_PowerDiff 0x28
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#define EEPROM_ThermalMeter 0x29
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#define EEPROM_TxPwDiff_CrystalCap 0x2A
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#define EEPROM_TxPwIndex_CCK 0x2C
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#define EEPROM_TxPwIndex_OFDM_24G 0x3A
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#define EEPROM_Default_TxPowerLevel 0x10
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#define EEPROM_IC_VER 0x7d
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#define EEPROM_CRC 0x7e
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#define EEPROM_CID_DEFAULT 0x0
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#define EEPROM_CID_CAMEO 0x1
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#define EEPROM_CID_RUNTOP 0x2
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#define EEPROM_CID_Senao 0x3
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#define EEPROM_CID_TOSHIBA 0x4
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#define EEPROM_CID_NetCore 0x5
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#define EEPROM_CID_Nettronix 0x6
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#define EEPROM_CID_Pronet 0x7
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#define EEPROM_CID_DLINK 0x8
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#define EEPROM_CID_WHQL 0xFE
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enum _RTL8192Pci_HW {
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MAC0 = 0x000,
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MAC1 = 0x001,
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MAC2 = 0x002,
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MAC3 = 0x003,
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MAC4 = 0x004,
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MAC5 = 0x005,
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PCIF = 0x009,
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#define MXDMA2_16bytes 0x000
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#define MXDMA2_32bytes 0x001
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#define MXDMA2_64bytes 0x010
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#define MXDMA2_128bytes 0x011
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#define MXDMA2_256bytes 0x100
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#define MXDMA2_512bytes 0x101
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#define MXDMA2_1024bytes 0x110
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#define MXDMA2_NoLimit 0x7
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#define MULRW_SHIFT 3
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#define MXDMA2_RX_SHIFT 4
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#define MXDMA2_TX_SHIFT 0
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PMR = 0x00c,
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EPROM_CMD = 0x00e,
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#define EPROM_CMD_RESERVED_MASK BIT5
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#define EPROM_CMD_9356SEL BIT4
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#define EPROM_CMD_OPERATING_MODE_SHIFT 6
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#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
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#define EPROM_CMD_CONFIG 0x3
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#define EPROM_CMD_NORMAL 0
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#define EPROM_CMD_LOAD 1
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#define EPROM_CMD_PROGRAM 2
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#define EPROM_CS_BIT 3
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#define EPROM_CK_BIT 2
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#define EPROM_W_BIT 1
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#define EPROM_R_BIT 0
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AFR = 0x010,
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#define AFR_CardBEn (1<<0)
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#define AFR_CLKRUN_SEL (1<<1)
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#define AFR_FuncRegEn (1<<2)
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ANAPAR = 0x17,
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#define BB_GLOBAL_RESET_BIT 0x1
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BB_GLOBAL_RESET = 0x020,
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BSSIDR = 0x02E,
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CMDR = 0x037,
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#define CR_RST 0x10
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#define CR_RE 0x08
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#define CR_TE 0x04
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#define CR_MulRW 0x01
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SIFS = 0x03E,
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TCR = 0x040,
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RCR = 0x044,
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#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
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BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
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#define RCR_ONLYERLPKT BIT31
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#define RCR_ENCS2 BIT30
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#define RCR_ENCS1 BIT29
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#define RCR_ENMBID BIT27
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#define RCR_ACKTXBW (BIT24|BIT25)
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#define RCR_CBSSID BIT23
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#define RCR_APWRMGT BIT22
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#define RCR_ADD3 BIT21
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#define RCR_AMF BIT20
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#define RCR_ACF BIT19
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#define RCR_ADF BIT18
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#define RCR_RXFTH BIT13
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#define RCR_AICV BIT12
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#define RCR_ACRC32 BIT5
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#define RCR_AB BIT3
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#define RCR_AM BIT2
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#define RCR_APM BIT1
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#define RCR_AAP BIT0
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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SLOT_TIME = 0x049,
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ACK_TIMEOUT = 0x04c,
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PIFS_TIME = 0x04d,
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USTIME = 0x04e,
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EDCAPARA_BE = 0x050,
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EDCAPARA_BK = 0x054,
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EDCAPARA_VO = 0x058,
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EDCAPARA_VI = 0x05C,
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#define AC_PARAM_TXOP_LIMIT_OFFSET 16
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#define AC_PARAM_ECW_MAX_OFFSET 12
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#define AC_PARAM_ECW_MIN_OFFSET 8
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#define AC_PARAM_AIFS_OFFSET 0
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RFPC = 0x05F,
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CWRR = 0x060,
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BCN_TCFG = 0x062,
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#define BCN_TCFG_CW_SHIFT 8
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#define BCN_TCFG_IFS 0
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BCN_INTERVAL = 0x070,
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ATIMWND = 0x072,
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BCN_DRV_EARLY_INT = 0x074,
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#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8
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#define BCN_DRV_EARLY_INT_TIME_SHIFT 0
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BCN_DMATIME = 0x076,
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BCN_ERR_THRESH = 0x078,
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RWCAM = 0x0A0,
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#define CAM_CM_SecCAMPolling BIT31
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#define CAM_CM_SecCAMClr BIT30
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#define CAM_CM_SecCAMWE BIT16
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#define CAM_VALID BIT15
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#define CAM_NOTVALID 0x0000
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#define CAM_USEDK BIT5
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#define CAM_NONE 0x0
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#define CAM_WEP40 0x01
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#define CAM_TKIP 0x02
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#define CAM_AES 0x04
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#define CAM_WEP104 0x05
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#define TOTAL_CAM_ENTRY 32
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#define CAM_CONFIG_USEDK true
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#define CAM_CONFIG_NO_USEDK false
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#define CAM_WRITE BIT16
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#define CAM_READ 0x00000000
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#define CAM_POLLINIG BIT31
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#define SCR_UseDK 0x01
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WCAMI = 0x0A4,
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RCAMO = 0x0A8,
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SECR = 0x0B0,
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#define SCR_TxUseDK BIT0
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#define SCR_RxUseDK BIT1
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#define SCR_TxEncEnable BIT2
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#define SCR_RxDecEnable BIT3
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#define SCR_SKByA2 BIT4
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#define SCR_NoSKMC BIT5
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SWREGULATOR = 0x0BD,
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INTA_MASK = 0x0f4,
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#define IMR8190_DISABLED 0x0
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#define IMR_ATIMEND BIT28
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#define IMR_TBDOK BIT27
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#define IMR_TBDER BIT26
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#define IMR_TXFOVW BIT15
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#define IMR_TIMEOUT0 BIT14
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#define IMR_BcnInt BIT13
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#define IMR_RXFOVW BIT12
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#define IMR_RDU BIT11
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#define IMR_RXCMDOK BIT10
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#define IMR_BDOK BIT9
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#define IMR_HIGHDOK BIT8
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#define IMR_COMDOK BIT7
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#define IMR_MGNTDOK BIT6
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#define IMR_HCCADOK BIT5
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#define IMR_BKDOK BIT4
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#define IMR_BEDOK BIT3
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#define IMR_VIDOK BIT2
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#define IMR_VODOK BIT1
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#define IMR_ROK BIT0
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ISR = 0x0f8,
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TPPoll = 0x0fd,
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#define TPPoll_BKQ BIT0
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#define TPPoll_BEQ BIT1
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#define TPPoll_VIQ BIT2
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#define TPPoll_VOQ BIT3
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#define TPPoll_BQ BIT4
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#define TPPoll_CQ BIT5
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#define TPPoll_MQ BIT6
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#define TPPoll_HQ BIT7
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#define TPPoll_HCCAQ BIT8
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#define TPPoll_StopBK BIT9
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#define TPPoll_StopBE BIT10
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#define TPPoll_StopVI BIT11
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#define TPPoll_StopVO BIT12
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#define TPPoll_StopMgt BIT13
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#define TPPoll_StopHigh BIT14
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#define TPPoll_StopHCCA BIT15
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#define TPPoll_SHIFT 8
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PSR = 0x0ff,
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#define PSR_GEN 0x0
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#define PSR_CPU 0x1
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CPU_GEN = 0x100,
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BB_RESET = 0x101,
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#define CPU_CCK_LOOPBACK 0x00030000
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#define CPU_GEN_SYSTEM_RESET 0x00000001
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#define CPU_GEN_FIRMWARE_RESET 0x00000008
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#define CPU_GEN_BOOT_RDY 0x00000010
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#define CPU_GEN_FIRM_RDY 0x00000020
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#define CPU_GEN_PUT_CODE_OK 0x00000080
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#define CPU_GEN_BB_RST 0x00000100
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#define CPU_GEN_PWR_STB_CPU 0x00000004
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#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
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#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
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#define CPU_GEN_GPIO_UART 0x00007000
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LED1Cfg = 0x154,
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LED0Cfg = 0x155,
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AcmAvg = 0x170,
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AcmHwCtrl = 0x171,
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#define AcmHw_HwEn BIT0
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#define AcmHw_BeqEn BIT1
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#define AcmHw_ViqEn BIT2
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#define AcmHw_VoqEn BIT3
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#define AcmHw_BeqStatus BIT4
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#define AcmHw_ViqStatus BIT5
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#define AcmHw_VoqStatus BIT6
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AcmFwCtrl = 0x172,
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#define AcmFw_BeqStatus BIT0
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#define AcmFw_ViqStatus BIT1
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#define AcmFw_VoqStatus BIT2
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VOAdmTime = 0x174,
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VIAdmTime = 0x178,
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BEAdmTime = 0x17C,
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RQPN1 = 0x180,
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RQPN2 = 0x184,
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RQPN3 = 0x188,
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QPRR = 0x1E0,
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QPNR = 0x1F0,
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BQDA = 0x200,
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HQDA = 0x204,
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CQDA = 0x208,
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MQDA = 0x20C,
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HCCAQDA = 0x210,
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VOQDA = 0x214,
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VIQDA = 0x218,
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BEQDA = 0x21C,
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BKQDA = 0x220,
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RCQDA = 0x224,
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RDQDA = 0x228,
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MAR0 = 0x240,
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MAR4 = 0x244,
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CCX_PERIOD = 0x250,
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CLM_RESULT = 0x251,
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NHM_PERIOD = 0x252,
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NHM_THRESHOLD0 = 0x253,
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NHM_THRESHOLD1 = 0x254,
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NHM_THRESHOLD2 = 0x255,
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NHM_THRESHOLD3 = 0x256,
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NHM_THRESHOLD4 = 0x257,
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NHM_THRESHOLD5 = 0x258,
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NHM_THRESHOLD6 = 0x259,
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MCTRL = 0x25A,
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NHM_RPI_COUNTER0 = 0x264,
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NHM_RPI_COUNTER1 = 0x265,
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NHM_RPI_COUNTER2 = 0x266,
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NHM_RPI_COUNTER3 = 0x267,
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NHM_RPI_COUNTER4 = 0x268,
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NHM_RPI_COUNTER5 = 0x269,
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NHM_RPI_COUNTER6 = 0x26A,
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NHM_RPI_COUNTER7 = 0x26B,
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WFCRC0 = 0x2f0,
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WFCRC1 = 0x2f4,
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WFCRC2 = 0x2f8,
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BW_OPMODE = 0x300,
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#define BW_OPMODE_11J BIT0
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#define BW_OPMODE_5G BIT1
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#define BW_OPMODE_20MHZ BIT2
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IC_VERRSION = 0x301,
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MSR = 0x303,
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#define MSR_LINK_MASK ((1<<0)|(1<<1))
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#define MSR_LINK_MANAGED 2
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#define MSR_LINK_NONE 0
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#define MSR_LINK_SHIFT 0
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#define MSR_LINK_ADHOC 1
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#define MSR_LINK_MASTER 3
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#define MSR_LINK_ENEDCA (1<<4)
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#define MSR_NOLINK 0x00
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#define MSR_ADHOC 0x01
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#define MSR_INFRA 0x02
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#define MSR_AP 0x03
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RETRY_LIMIT = 0x304,
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#define RETRY_LIMIT_SHORT_SHIFT 8
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#define RETRY_LIMIT_LONG_SHIFT 0
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TSFR = 0x308,
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RRSR = 0x310,
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#define RRSR_RSC_OFFSET 21
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#define RRSR_SHORT_OFFSET 23
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#define RRSR_RSC_DUPLICATE 0x600000
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#define RRSR_RSC_UPSUBCHNL 0x400000
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#define RRSR_RSC_LOWSUBCHNL 0x200000
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#define RRSR_SHORT 0x800000
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#define RRSR_1M BIT0
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#define RRSR_2M BIT1
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#define RRSR_5_5M BIT2
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#define RRSR_11M BIT3
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#define RRSR_6M BIT4
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#define RRSR_9M BIT5
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#define RRSR_12M BIT6
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#define RRSR_18M BIT7
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#define RRSR_24M BIT8
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#define RRSR_36M BIT9
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#define RRSR_48M BIT10
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#define RRSR_54M BIT11
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#define RRSR_MCS0 BIT12
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#define RRSR_MCS1 BIT13
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#define RRSR_MCS2 BIT14
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#define RRSR_MCS3 BIT15
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#define RRSR_MCS4 BIT16
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#define RRSR_MCS5 BIT17
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#define RRSR_MCS6 BIT18
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#define RRSR_MCS7 BIT19
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#define BRSR_AckShortPmb BIT23
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UFWP = 0x318,
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RATR0 = 0x320,
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#define RATR_1M 0x00000001
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#define RATR_2M 0x00000002
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#define RATR_55M 0x00000004
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#define RATR_11M 0x00000008
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#define RATR_6M 0x00000010
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#define RATR_9M 0x00000020
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#define RATR_12M 0x00000040
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#define RATR_18M 0x00000080
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#define RATR_24M 0x00000100
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#define RATR_36M 0x00000200
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#define RATR_48M 0x00000400
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#define RATR_54M 0x00000800
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#define RATR_MCS0 0x00001000
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#define RATR_MCS1 0x00002000
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#define RATR_MCS2 0x00004000
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#define RATR_MCS3 0x00008000
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#define RATR_MCS4 0x00010000
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#define RATR_MCS5 0x00020000
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#define RATR_MCS6 0x00040000
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#define RATR_MCS7 0x00080000
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#define RATR_MCS8 0x00100000
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#define RATR_MCS9 0x00200000
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#define RATR_MCS10 0x00400000
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#define RATR_MCS11 0x00800000
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#define RATR_MCS12 0x01000000
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#define RATR_MCS13 0x02000000
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#define RATR_MCS14 0x04000000
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#define RATR_MCS15 0x08000000
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#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
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#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
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RATR_24M | RATR_36M | RATR_48M | RATR_54M)
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#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
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RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
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RATR_MCS6 | RATR_MCS7)
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#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
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RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
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RATR_MCS14|RATR_MCS15)
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DRIVER_RSSI = 0x32c,
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MCS_TXAGC = 0x340,
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CCK_TXAGC = 0x348,
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MacBlkCtrl = 0x403,
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}
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;
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#define GPI 0x108
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#define GPO 0x109
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#define GPE 0x10a
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#define HWSET_MAX_SIZE_92S 128
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#define ANAPAR_FOR_8192PciE 0x17
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#endif
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