/*************************************************************************/ /*!
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@File
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@Title Device specific power routines
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Device specific functions
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#include <stddef.h>
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#include "rgxpower.h"
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#include "rgxinit.h"
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#include "rgx_fwif_km.h"
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#include "rgxfwutils.h"
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#include "pdump_km.h"
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#include "pvr_debug.h"
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#include "osfunc.h"
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#include "rgxdebug.h"
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#include "devicemem.h"
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#include "devicemem_pdump.h"
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#include "rgxtimecorr.h"
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#include "devicemem_utils.h"
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#include "htbserver.h"
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#include "rgxstartstop.h"
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#include "sync.h"
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#include "lists.h"
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#if defined(PVRSRV_ENABLE_PROCESS_STATS)
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#include "process_stats.h"
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#endif
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#if defined(PVR_DVFS)
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#include "pvr_dvfs_device.h"
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#endif
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static PVRSRV_ERROR RGXFWNotifyHostTimeout(PVRSRV_RGXDEV_INFO *psDevInfo)
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{
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PVRSRV_ERROR eError;
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RGXFWIF_KCCB_CMD sCmd;
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RGXFWIF_RUNTIME_CFG *psRuntimeCfg = psDevInfo->psRGXFWIfRuntimeCfg;
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/* Send the Timeout notification to the FW */
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/* Extending the APM Latency Change command structure with the notification boolean for
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backwards compatibility reasons */
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sCmd.eCmdType = RGXFWIF_KCCB_CMD_POW;
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sCmd.uCmdData.sPowData.ePowType = RGXFWIF_POW_APM_LATENCY_CHANGE;
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sCmd.uCmdData.sPowData.uPoweReqData.ui32ActivePMLatencyms = psRuntimeCfg->ui32ActivePMLatencyms;
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sCmd.uCmdData.sPowData.bNotifyTimeout = IMG_TRUE;
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/* Ensure the new APM latency is written to memory before requesting the FW to read it */
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OSMemoryBarrier();
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eError = RGXSendCommand(psDevInfo,
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RGXFWIF_DM_GP,
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&sCmd,
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sizeof(sCmd),
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PDUMP_FLAGS_NONE);
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return eError;
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}
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static void _RGXUpdateGPUUtilStats(PVRSRV_RGXDEV_INFO *psDevInfo)
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{
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RGXFWIF_GPU_UTIL_FWCB *psUtilFWCb;
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IMG_UINT64 *paui64StatsCounters;
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IMG_UINT64 ui64LastPeriod;
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IMG_UINT64 ui64LastState;
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IMG_UINT64 ui64LastTime;
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IMG_UINT64 ui64TimeNow;
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psUtilFWCb = psDevInfo->psRGXFWIfGpuUtilFWCb;
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paui64StatsCounters = &psUtilFWCb->aui64StatsCounters[0];
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OSLockAcquire(psDevInfo->hGPUUtilLock);
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ui64TimeNow = RGXFWIF_GPU_UTIL_GET_TIME(OSClockns64());
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/* Update counters to account for the time since the last update */
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ui64LastState = RGXFWIF_GPU_UTIL_GET_STATE(psUtilFWCb->ui64LastWord);
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ui64LastTime = RGXFWIF_GPU_UTIL_GET_TIME(psUtilFWCb->ui64LastWord);
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ui64LastPeriod = RGXFWIF_GPU_UTIL_GET_PERIOD(ui64TimeNow, ui64LastTime);
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paui64StatsCounters[ui64LastState] += ui64LastPeriod;
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/* Update state and time of the latest update */
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psUtilFWCb->ui64LastWord = RGXFWIF_GPU_UTIL_MAKE_WORD(ui64TimeNow, ui64LastState);
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OSLockRelease(psDevInfo->hGPUUtilLock);
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}
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static INLINE PVRSRV_ERROR RGXDoStop(PVRSRV_DEVICE_NODE *psDeviceNode)
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{
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PVRSRV_ERROR eError;
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#if defined(SUPPORT_TRUSTED_DEVICE) && !defined(NO_HARDWARE)
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PVRSRV_DEVICE_CONFIG *psDevConfig = psDeviceNode->psDevConfig;
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if (psDevConfig->pfnTDRGXStop == NULL)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPrePowerState: TDRGXStop not implemented!"));
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return PVRSRV_ERROR_NOT_IMPLEMENTED;
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}
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eError = psDevConfig->pfnTDRGXStop(psDevConfig->hSysData);
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#else
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PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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eError = RGXStop(&psDevInfo->sPowerParams);
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#endif
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return eError;
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}
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/*
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RGXPrePowerState
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*/
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PVRSRV_ERROR RGXPrePowerState (IMG_HANDLE hDevHandle,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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PVRSRV_ERROR eError = PVRSRV_OK;
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if ((eNewPowerState != eCurrentPowerState) &&
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(eNewPowerState != PVRSRV_DEV_POWER_STATE_ON))
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{
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PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
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PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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RGXFWIF_KCCB_CMD sPowCmd;
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RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
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/* Send the Power off request to the FW */
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sPowCmd.eCmdType = RGXFWIF_KCCB_CMD_POW;
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sPowCmd.uCmdData.sPowData.ePowType = RGXFWIF_POW_OFF_REQ;
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sPowCmd.uCmdData.sPowData.uPoweReqData.bForced = bForced;
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eError = SyncPrimSet(psDevInfo->psPowSyncPrim, 0);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,"%s: Failed to set Power sync prim",
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__FUNCTION__));
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return eError;
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}
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eError = RGXSendCommand(psDevInfo,
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RGXFWIF_DM_GP,
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&sPowCmd,
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sizeof(sPowCmd),
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PDUMP_FLAGS_NONE);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,"RGXPrePowerState: Failed to send Power off request"));
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return eError;
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}
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/* Wait for the firmware to complete processing. It cannot use PVRSRVWaitForValueKM as it relies
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on the EventObject which is signalled in this MISR */
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eError = PVRSRVPollForValueKM(psDevInfo->psPowSyncPrim->pui32LinAddr, 0x1, 0xFFFFFFFF);
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/* Check the Power state after the answer */
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if (eError == PVRSRV_OK)
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{
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/* Finally, de-initialise some registers. */
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if (psFWTraceBuf->ePowState == RGXFWIF_POW_OFF)
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{
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#if !defined(NO_HARDWARE)
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IMG_UINT32 ui32TID;
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for (ui32TID = 0; ui32TID < RGXFW_THREAD_NUM; ui32TID++)
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{
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/* Wait for the pending META/MIPS to host interrupts to come back. */
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eError = PVRSRVPollForValueKM(&psDevInfo->aui32SampleIRQCount[ui32TID],
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psFWTraceBuf->aui32InterruptCount[ui32TID],
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0xffffffff);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, \
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"RGXPrePowerState: Wait for pending interrupts failed. Thread %u: Host:%u, FW: %u", \
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ui32TID, \
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psDevInfo->aui32SampleIRQCount[ui32TID], \
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psFWTraceBuf->aui32InterruptCount[ui32TID]));
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RGX_WaitForInterruptsTimeout(psDevInfo);
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break;
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}
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}
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#endif /* NO_HARDWARE */
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/* Update GPU frequency and timer correlation related data */
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RGXGPUFreqCalibratePrePowerOff(psDeviceNode);
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/* Update GPU state counters */
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_RGXUpdateGPUUtilStats(psDevInfo);
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#if defined(PVR_DVFS)
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eError = SuspendDVFS();
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,"RGXPrePowerState: Failed to suspend DVFS"));
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return eError;
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}
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#endif
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psDevInfo->bRGXPowered = IMG_FALSE;
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eError = RGXDoStop(psDeviceNode);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPrePowerState: RGXDoStop failed (%s)",
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PVRSRVGetErrorStringKM(eError)));
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eError = PVRSRV_ERROR_DEVICE_POWER_CHANGE_FAILURE;
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}
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}
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else
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{
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/* the sync was updated bu the pow state isn't off -> the FW denied the transition */
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eError = PVRSRV_ERROR_DEVICE_POWER_CHANGE_DENIED;
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if (bForced)
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{ /* It is an error for a forced request to be denied */
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PVR_DPF((PVR_DBG_ERROR,"RGXPrePowerState: Failure to power off during a forced power off. FW: %d", psFWTraceBuf->ePowState));
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}
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}
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}
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else if (eError == PVRSRV_ERROR_TIMEOUT)
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{
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/* timeout waiting for the FW to ack the request: return timeout */
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PVR_DPF((PVR_DBG_WARNING,"RGXPrePowerState: Timeout waiting for powoff ack from the FW"));
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}
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else
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{
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PVR_DPF((PVR_DBG_ERROR,"RGXPrePowerState: Error waiting for powoff ack from the FW (%s)", PVRSRVGetErrorStringKM(eError)));
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eError = PVRSRV_ERROR_DEVICE_POWER_CHANGE_FAILURE;
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}
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}
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return eError;
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}
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static INLINE PVRSRV_ERROR RGXDoStart(PVRSRV_DEVICE_NODE *psDeviceNode)
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{
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PVRSRV_ERROR eError;
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#if defined(SUPPORT_TRUSTED_DEVICE) && !defined(NO_HARDWARE)
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PVRSRV_DEVICE_CONFIG *psDevConfig = psDeviceNode->psDevConfig;
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if (psDevConfig->pfnTDRGXStart == NULL)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPostPowerState: TDRGXStart not implemented!"));
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return PVRSRV_ERROR_NOT_IMPLEMENTED;
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}
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eError = psDevConfig->pfnTDRGXStart(psDevConfig->hSysData);
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#else
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PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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eError = RGXStart(&psDevInfo->sPowerParams);
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#endif
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return eError;
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}
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/*
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RGXPostPowerState
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*/
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PVRSRV_ERROR RGXPostPowerState (IMG_HANDLE hDevHandle,
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PVRSRV_DEV_POWER_STATE eNewPowerState,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState,
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IMG_BOOL bForced)
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{
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if ((eNewPowerState != eCurrentPowerState) &&
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(eCurrentPowerState != PVRSRV_DEV_POWER_STATE_ON))
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{
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PVRSRV_ERROR eError;
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PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
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PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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RGXFWIF_INIT *psRGXFWInit;
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if (eCurrentPowerState == PVRSRV_DEV_POWER_STATE_OFF)
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{
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/* Update GPU frequency and timer correlation related data */
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RGXGPUFreqCalibratePostPowerOn(psDeviceNode);
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/* Update GPU state counters */
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_RGXUpdateGPUUtilStats(psDevInfo);
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eError = RGXDoStart(psDeviceNode);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,"RGXPostPowerState: RGXDoStart failed"));
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return eError;
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}
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OSMemoryBarrier();
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#if defined(SUPPORT_EXTRA_METASP_DEBUG)
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eError = ValidateFWImageWithSP(psDevInfo);
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if (eError != PVRSRV_OK) return eError;
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#endif
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eError = DevmemAcquireCpuVirtAddr(psDevInfo->psRGXFWIfInitMemDesc,
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(void **)&psRGXFWInit);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,
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"RGXPostPowerState: Failed to acquire kernel fw if ctl (%u)",
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eError));
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return eError;
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}
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/*
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* Check whether the FW has started by polling on bFirmwareStarted flag
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*/
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if (PVRSRVPollForValueKM((IMG_UINT32 *)&psRGXFWInit->bFirmwareStarted,
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IMG_TRUE,
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0xFFFFFFFF) != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPostPowerState: Polling for 'FW started' flag failed."));
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eError = PVRSRV_ERROR_TIMEOUT;
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/*
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* When bFirmwareStarted fails some info maybe gained by doing the following
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* debug dump but unfortunately it could lockup some cores or cause other power
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* lock issues. The code is placed here to provide a possible example approach
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* when all other ideas have been tried.
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*/
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/*{
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PVRSRV_POWER_DEV *psPowerDev = psDeviceNode->psPowerDev;
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if (psPowerDev)
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{
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PVRSRV_DEV_POWER_STATE eOldPowerState = psPowerDev->eCurrentPowerState;
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PVRSRVPowerUnlock(psDeviceNode);
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psPowerDev->eCurrentPowerState = PVRSRV_DEV_POWER_STATE_ON;
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RGXDumpDebugInfo(NULL, psDeviceNode->pvDevice);
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psPowerDev->eCurrentPowerState = eOldPowerState;
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PVRSRVPowerLock(psDeviceNode);
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}
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}*/
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DevmemReleaseCpuVirtAddr(psDevInfo->psRGXFWIfInitMemDesc);
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return eError;
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}
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#if defined(PDUMP)
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PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "Wait for the Firmware to start.");
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eError = DevmemPDumpDevmemPol32(psDevInfo->psRGXFWIfInitMemDesc,
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offsetof(RGXFWIF_INIT, bFirmwareStarted),
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IMG_TRUE,
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0xFFFFFFFFU,
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PDUMP_POLL_OPERATOR_EQUAL,
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PDUMP_FLAGS_CONTINUOUS);
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,
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"RGXPostPowerState: problem pdumping POL for psRGXFWIfInitMemDesc (%d)",
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eError));
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DevmemReleaseCpuVirtAddr(psDevInfo->psRGXFWIfInitMemDesc);
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return eError;
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}
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#endif
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#if defined(PVRSRV_ENABLE_PROCESS_STATS)
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SetFirmwareStartTime(psRGXFWInit->ui32FirmwareStartedTimeStamp);
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#endif
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HTBSyncPartitionMarker(psRGXFWInit->ui32MarkerVal);
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DevmemReleaseCpuVirtAddr(psDevInfo->psRGXFWIfInitMemDesc);
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psDevInfo->bRGXPowered = IMG_TRUE;
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#if defined(PVR_DVFS)
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eError = ResumeDVFS();
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if (eError != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR,"RGXPostPowerState: Failed to resume DVFS"));
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return eError;
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}
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#endif
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}
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}
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PDUMPCOMMENT("RGXPostPowerState: Current state: %d, New state: %d", eCurrentPowerState, eNewPowerState);
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return PVRSRV_OK;
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}
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|
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/*
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RGXPreClockSpeedChange
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*/
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PVRSRV_ERROR RGXPreClockSpeedChange (IMG_HANDLE hDevHandle,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState)
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{
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PVRSRV_ERROR eError = PVRSRV_OK;
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PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
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PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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RGX_DATA *psRGXData = (RGX_DATA*)psDeviceNode->psDevConfig->hDevData;
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RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
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PVR_UNREFERENCED_PARAMETER(psRGXData);
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PVR_DPF((PVR_DBG_MESSAGE,"RGXPreClockSpeedChange: RGX clock speed was %uHz",
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psRGXData->psRGXTimingInfo->ui32CoreClockSpeed));
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if ((eCurrentPowerState != PVRSRV_DEV_POWER_STATE_OFF)
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&& (psFWTraceBuf->ePowState != RGXFWIF_POW_OFF))
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{
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/* Update GPU frequency and timer correlation related data */
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RGXGPUFreqCalibratePreClockSpeedChange(psDeviceNode);
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}
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return eError;
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}
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|
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/*
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RGXPostClockSpeedChange
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*/
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PVRSRV_ERROR RGXPostClockSpeedChange (IMG_HANDLE hDevHandle,
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PVRSRV_DEV_POWER_STATE eCurrentPowerState)
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{
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PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
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RGX_DATA *psRGXData = (RGX_DATA*)psDeviceNode->psDevConfig->hDevData;
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PVRSRV_ERROR eError = PVRSRV_OK;
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RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
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IMG_UINT32 ui32NewClockSpeed = psRGXData->psRGXTimingInfo->ui32CoreClockSpeed;
|
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/* Update runtime configuration with the new value */
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psDevInfo->psRGXFWIfRuntimeCfg->ui32CoreClockSpeed = ui32NewClockSpeed;
|
|
if ((eCurrentPowerState != PVRSRV_DEV_POWER_STATE_OFF)
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&& (psFWTraceBuf->ePowState != RGXFWIF_POW_OFF))
|
{
|
RGXFWIF_KCCB_CMD sCOREClkSpeedChangeCmd;
|
|
RGXGPUFreqCalibratePostClockSpeedChange(psDeviceNode, ui32NewClockSpeed);
|
|
sCOREClkSpeedChangeCmd.eCmdType = RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE;
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sCOREClkSpeedChangeCmd.uCmdData.sCORECLKSPEEDCHANGEData.ui32NewClockSpeed = ui32NewClockSpeed;
|
|
/* Ensure the new clock speed is written to memory before requesting the FW to read it */
|
OSMemoryBarrier();
|
|
PDUMPCOMMENT("Scheduling CORE clock speed change command");
|
|
PDUMPPOWCMDSTART();
|
eError = RGXSendCommand(psDeviceNode->pvDevice,
|
RGXFWIF_DM_GP,
|
&sCOREClkSpeedChangeCmd,
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sizeof(sCOREClkSpeedChangeCmd),
|
PDUMP_FLAGS_NONE);
|
PDUMPPOWCMDEND();
|
|
if (eError != PVRSRV_OK)
|
{
|
PDUMPCOMMENT("Scheduling CORE clock speed change command failed");
|
PVR_DPF((PVR_DBG_ERROR, "RGXPostClockSpeedChange: Scheduling KCCB command failed. Error:%u", eError));
|
return eError;
|
}
|
|
PVR_DPF((PVR_DBG_MESSAGE,"RGXPostClockSpeedChange: RGX clock speed changed to %uHz",
|
psRGXData->psRGXTimingInfo->ui32CoreClockSpeed));
|
}
|
|
return eError;
|
}
|
|
|
/*!
|
******************************************************************************
|
|
@Function RGXDustCountChange
|
|
@Description
|
|
Does change of number of DUSTs
|
|
@Input hDevHandle : RGX Device Node
|
@Input ui32NumberOfDusts : Number of DUSTs to make transition to
|
|
@Return PVRSRV_ERROR :
|
|
******************************************************************************/
|
PVRSRV_ERROR RGXDustCountChange(IMG_HANDLE hDevHandle,
|
IMG_UINT32 ui32NumberOfDusts)
|
{
|
|
PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
|
PVRSRV_ERROR eError;
|
RGXFWIF_KCCB_CMD sDustCountChange;
|
IMG_UINT32 ui32MaxAvailableDusts = MAX(1, (psDevInfo->sDevFeatureCfg.ui32NumClusters/2));
|
RGXFWIF_RUNTIME_CFG *psRuntimeCfg = psDevInfo->psRGXFWIfRuntimeCfg;
|
|
if (ui32NumberOfDusts > ui32MaxAvailableDusts)
|
{
|
eError = PVRSRV_ERROR_INVALID_PARAMS;
|
PVR_DPF((PVR_DBG_ERROR,
|
"RGXDustCountChange: Invalid number of DUSTs (%u) while expecting value within <0,%u>. Error:%u",
|
ui32NumberOfDusts,
|
ui32MaxAvailableDusts,
|
eError));
|
return eError;
|
}
|
|
#if defined(FIX_HW_BRN_59042)
|
if (ui32NumberOfDusts < ui32MaxAvailableDusts && (ui32NumberOfDusts & 0x1))
|
{
|
PVR_DPF((PVR_DBG_ERROR,
|
"RGXDustCountChange: Invalid number of DUSTs (%u) due to HW restriction. Allowed values are :-",
|
ui32NumberOfDusts));
|
switch (ui32MaxAvailableDusts)
|
{
|
case 2: PVR_DPF((PVR_DBG_ERROR, "0, 2")); break;
|
case 3: PVR_DPF((PVR_DBG_ERROR, "0, 2, 3")); break;
|
case 4: PVR_DPF((PVR_DBG_ERROR, "0, 2, 4")); break;
|
case 5: PVR_DPF((PVR_DBG_ERROR, "0, 2, 4, 5")); break;
|
case 6: PVR_DPF((PVR_DBG_ERROR, "0, 2, 4, 6")); break;
|
default: break;
|
}
|
return PVRSRV_ERROR_INVALID_PARAMS;
|
}
|
#endif
|
|
psRuntimeCfg->ui32DefaultDustsNumInit = ui32NumberOfDusts;
|
|
#if !defined(NO_HARDWARE)
|
{
|
RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
|
|
if (psFWTraceBuf->ePowState == RGXFWIF_POW_OFF)
|
{
|
return PVRSRV_OK;
|
}
|
|
if (psFWTraceBuf->ePowState != RGXFWIF_POW_FORCED_IDLE)
|
{
|
eError = PVRSRV_ERROR_DEVICE_POWER_CHANGE_DENIED;
|
PVR_DPF((PVR_DBG_ERROR,"RGXDustCountChange: Attempt to change dust count when not IDLE"));
|
return eError;
|
}
|
}
|
#endif
|
|
eError = SyncPrimSet(psDevInfo->psPowSyncPrim, 0);
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"%s: Failed to set Power sync prim",
|
__FUNCTION__));
|
return eError;
|
}
|
|
sDustCountChange.eCmdType = RGXFWIF_KCCB_CMD_POW;
|
sDustCountChange.uCmdData.sPowData.ePowType = RGXFWIF_POW_NUMDUST_CHANGE;
|
sDustCountChange.uCmdData.sPowData.uPoweReqData.ui32NumOfDusts = ui32NumberOfDusts;
|
|
PDUMPCOMMENT("Scheduling command to change Dust Count to %u", ui32NumberOfDusts);
|
eError = RGXSendCommand(psDeviceNode->pvDevice,
|
RGXFWIF_DM_GP,
|
&sDustCountChange,
|
sizeof(sDustCountChange),
|
PDUMP_FLAGS_NONE);
|
|
if (eError != PVRSRV_OK)
|
{
|
PDUMPCOMMENT("Scheduling command to change Dust Count failed. Error:%u", eError);
|
PVR_DPF((PVR_DBG_ERROR, "RGXDustCountChange: Scheduling KCCB to change Dust Count failed. Error:%u", eError));
|
return eError;
|
}
|
|
/* Wait for the firmware to answer. */
|
eError = PVRSRVPollForValueKM(psDevInfo->psPowSyncPrim->pui32LinAddr, 0x1, 0xFFFFFFFF);
|
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"RGXDustCountChange: Timeout waiting for idle request"));
|
return eError;
|
}
|
|
#if defined(PDUMP)
|
PDUMPCOMMENT("RGXDustCountChange: Poll for Kernel SyncPrim [0x%p] on DM %d ", psDevInfo->psPowSyncPrim->pui32LinAddr, RGXFWIF_DM_GP);
|
|
SyncPrimPDumpPol(psDevInfo->psPowSyncPrim,
|
1,
|
0xffffffff,
|
PDUMP_POLL_OPERATOR_EQUAL,
|
0);
|
#endif
|
|
return PVRSRV_OK;
|
}
|
/*
|
@Function RGXAPMLatencyChange
|
*/
|
PVRSRV_ERROR RGXAPMLatencyChange(IMG_HANDLE hDevHandle,
|
IMG_UINT32 ui32ActivePMLatencyms,
|
IMG_BOOL bActivePMLatencyPersistant)
|
{
|
|
PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
|
PVRSRV_ERROR eError;
|
RGXFWIF_RUNTIME_CFG *psRuntimeCfg = psDevInfo->psRGXFWIfRuntimeCfg;
|
PVRSRV_DEV_POWER_STATE ePowerState;
|
|
eError = PVRSRVPowerLock(psDeviceNode);
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"RGXAPMLatencyChange: Failed to acquire power lock"));
|
return eError;
|
}
|
|
/* Update runtime configuration with the new values */
|
psRuntimeCfg->ui32ActivePMLatencyms = ui32ActivePMLatencyms;
|
psRuntimeCfg->bActivePMLatencyPersistant = bActivePMLatencyPersistant;
|
|
eError = PVRSRVGetDevicePowerState(psDeviceNode, &ePowerState);
|
|
if ((eError == PVRSRV_OK) && (ePowerState != PVRSRV_DEV_POWER_STATE_OFF))
|
{
|
RGXFWIF_KCCB_CMD sActivePMLatencyChange;
|
sActivePMLatencyChange.eCmdType = RGXFWIF_KCCB_CMD_POW;
|
sActivePMLatencyChange.uCmdData.sPowData.bNotifyTimeout = IMG_FALSE;
|
sActivePMLatencyChange.uCmdData.sPowData.ePowType = RGXFWIF_POW_APM_LATENCY_CHANGE;
|
sActivePMLatencyChange.uCmdData.sPowData.uPoweReqData.ui32ActivePMLatencyms = ui32ActivePMLatencyms;
|
|
/* Ensure the new APM latency is written to memory before requesting the FW to read it */
|
OSMemoryBarrier();
|
|
PDUMPCOMMENT("Scheduling command to change APM latency to %u", ui32ActivePMLatencyms);
|
eError = RGXSendCommand(psDeviceNode->pvDevice,
|
RGXFWIF_DM_GP,
|
&sActivePMLatencyChange,
|
sizeof(sActivePMLatencyChange),
|
PDUMP_FLAGS_NONE);
|
|
if (eError != PVRSRV_OK)
|
{
|
PDUMPCOMMENT("Scheduling command to change APM latency failed. Error:%u", eError);
|
PVR_DPF((PVR_DBG_ERROR, "RGXAPMLatencyChange: Scheduling KCCB to change APM latency failed. Error:%u", eError));
|
return eError;
|
}
|
}
|
|
PVRSRVPowerUnlock(psDeviceNode);
|
|
return PVRSRV_OK;
|
}
|
|
/*
|
RGXActivePowerRequest
|
*/
|
PVRSRV_ERROR RGXActivePowerRequest(IMG_HANDLE hDevHandle)
|
{
|
PVRSRV_ERROR eError = PVRSRV_OK;
|
PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
|
RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
|
|
OSAcquireBridgeLock();
|
/* NOTE: If this function were to wait for event object attempt should be
|
made to prevent releasing bridge lock during sleep. Bridge lock should
|
be held during sleep. */
|
|
/* Powerlock to avoid further requests from racing with the FW hand-shake from now on
|
(previous kicks to this point are detected by the FW) */
|
eError = PVRSRVPowerLock(psDeviceNode);
|
if(eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,
|
"%s: Failed to acquire PowerLock (device: %p, error: %s)",
|
__func__, psDeviceNode, PVRSRVGetErrorStringKM(eError)));
|
goto _RGXActivePowerRequest_PowerLock_failed;
|
}
|
|
/* Check again for IDLE once we have the power lock */
|
if (psFWTraceBuf->ePowState == RGXFWIF_POW_IDLE)
|
{
|
|
psDevInfo->ui32ActivePMReqTotal++;
|
|
#if defined(PVRSRV_ENABLE_PROCESS_STATS)
|
SetFirmwareHandshakeIdleTime(RGXReadHWTimerReg(psDevInfo)-psFWTraceBuf->ui64StartIdleTime);
|
#endif
|
|
PDUMPPOWCMDSTART();
|
eError = PVRSRVSetDevicePowerStateKM(psDeviceNode,
|
PVRSRV_DEV_POWER_STATE_OFF,
|
IMG_FALSE); /* forced */
|
PDUMPPOWCMDEND();
|
|
if (eError == PVRSRV_OK)
|
{
|
psDevInfo->ui32ActivePMReqOk++;
|
}
|
else if (eError == PVRSRV_ERROR_DEVICE_POWER_CHANGE_DENIED)
|
{
|
psDevInfo->ui32ActivePMReqDenied++;
|
}
|
|
}
|
|
PVRSRVPowerUnlock(psDeviceNode);
|
|
_RGXActivePowerRequest_PowerLock_failed:
|
OSReleaseBridgeLock();
|
|
return eError;
|
|
}
|
/*
|
RGXForcedIdleRequest
|
*/
|
|
#define RGX_FORCED_IDLE_RETRY_COUNT 10
|
|
PVRSRV_ERROR RGXForcedIdleRequest(IMG_HANDLE hDevHandle, IMG_BOOL bDeviceOffPermitted)
|
{
|
PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
|
RGXFWIF_KCCB_CMD sPowCmd;
|
PVRSRV_ERROR eError;
|
IMG_UINT32 ui32RetryCount = 0;
|
|
#if !defined(NO_HARDWARE)
|
RGXFWIF_TRACEBUF *psFWTraceBuf = psDevInfo->psRGXFWIfTraceBuf;
|
|
/* Firmware already forced idle */
|
if (psFWTraceBuf->ePowState == RGXFWIF_POW_FORCED_IDLE)
|
{
|
return PVRSRV_OK;
|
}
|
|
/* Firmware is not powered. Sometimes this is permitted, for instance we were forcing idle to power down. */
|
if (psFWTraceBuf->ePowState == RGXFWIF_POW_OFF)
|
{
|
return (bDeviceOffPermitted) ? PVRSRV_OK : PVRSRV_ERROR_DEVICE_IDLE_REQUEST_DENIED;
|
}
|
#endif
|
|
eError = SyncPrimSet(psDevInfo->psPowSyncPrim, 0);
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"%s: Failed to set Power sync prim",
|
__FUNCTION__));
|
return eError;
|
}
|
sPowCmd.eCmdType = RGXFWIF_KCCB_CMD_POW;
|
sPowCmd.uCmdData.sPowData.ePowType = RGXFWIF_POW_FORCED_IDLE_REQ;
|
sPowCmd.uCmdData.sPowData.uPoweReqData.bCancelForcedIdle = IMG_FALSE;
|
|
PDUMPCOMMENT("RGXForcedIdleRequest: Sending forced idle command");
|
|
/* Send one forced IDLE command to GP */
|
eError = RGXSendCommand(psDevInfo,
|
RGXFWIF_DM_GP,
|
&sPowCmd,
|
sizeof(sPowCmd),
|
PDUMP_FLAGS_NONE);
|
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"RGXForcedIdleRequest: Failed to send idle request"));
|
return eError;
|
}
|
|
/* Wait for GPU to finish current workload */
|
do {
|
eError = PVRSRVPollForValueKM(psDevInfo->psPowSyncPrim->pui32LinAddr, 0x1, 0xFFFFFFFF);
|
if ((eError == PVRSRV_OK) || (ui32RetryCount == RGX_FORCED_IDLE_RETRY_COUNT))
|
{
|
break;
|
}
|
ui32RetryCount++;
|
PVR_DPF((PVR_DBG_WARNING,"RGXForcedIdleRequest: Request timeout. Retry %d of %d", ui32RetryCount, RGX_FORCED_IDLE_RETRY_COUNT));
|
} while (IMG_TRUE);
|
|
if (eError != PVRSRV_OK)
|
{
|
RGXFWNotifyHostTimeout(psDevInfo);
|
PVR_DPF((PVR_DBG_ERROR,"RGXForcedIdleRequest: Idle request failed. Firmware potentially left in forced idle state"));
|
return eError;
|
}
|
|
#if defined(PDUMP)
|
PDUMPCOMMENT("RGXForcedIdleRequest: Poll for Kernel SyncPrim [0x%p] on DM %d ", psDevInfo->psPowSyncPrim->pui32LinAddr, RGXFWIF_DM_GP);
|
|
SyncPrimPDumpPol(psDevInfo->psPowSyncPrim,
|
1,
|
0xffffffff,
|
PDUMP_POLL_OPERATOR_EQUAL,
|
0);
|
#endif
|
|
#if !defined(NO_HARDWARE)
|
/* Check the firmware state for idleness */
|
if (psFWTraceBuf->ePowState != RGXFWIF_POW_FORCED_IDLE)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"RGXForcedIdleRequest: Failed to force IDLE"));
|
|
return PVRSRV_ERROR_DEVICE_IDLE_REQUEST_DENIED;
|
}
|
#endif
|
|
return PVRSRV_OK;
|
}
|
|
/*
|
RGXCancelForcedIdleRequest
|
*/
|
PVRSRV_ERROR RGXCancelForcedIdleRequest(IMG_HANDLE hDevHandle)
|
{
|
PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
|
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
|
RGXFWIF_KCCB_CMD sPowCmd;
|
PVRSRV_ERROR eError = PVRSRV_OK;
|
|
eError = SyncPrimSet(psDevInfo->psPowSyncPrim, 0);
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"%s: Failed to set Power sync prim",
|
__FUNCTION__));
|
goto ErrorExit;
|
}
|
|
/* Send the IDLE request to the FW */
|
sPowCmd.eCmdType = RGXFWIF_KCCB_CMD_POW;
|
sPowCmd.uCmdData.sPowData.ePowType = RGXFWIF_POW_FORCED_IDLE_REQ;
|
sPowCmd.uCmdData.sPowData.uPoweReqData.bCancelForcedIdle = IMG_TRUE;
|
|
PDUMPCOMMENT("RGXForcedIdleRequest: Sending cancel forced idle command");
|
|
/* Send cancel forced IDLE command to GP */
|
eError = RGXSendCommand(psDevInfo,
|
RGXFWIF_DM_GP,
|
&sPowCmd,
|
sizeof(sPowCmd),
|
PDUMP_FLAGS_NONE);
|
|
if (eError != PVRSRV_OK)
|
{
|
PDUMPCOMMENT("RGXCancelForcedIdleRequest: Failed to send cancel IDLE request for DM%d", RGXFWIF_DM_GP);
|
goto ErrorExit;
|
}
|
|
/* Wait for the firmware to answer. */
|
eError = PVRSRVPollForValueKM(psDevInfo->psPowSyncPrim->pui32LinAddr, 1, 0xFFFFFFFF);
|
|
if (eError != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR,"RGXCancelForcedIdleRequest: Timeout waiting for cancel idle request"));
|
goto ErrorExit;
|
}
|
|
#if defined(PDUMP)
|
PDUMPCOMMENT("RGXCancelForcedIdleRequest: Poll for Kernel SyncPrim [0x%p] on DM %d ", psDevInfo->psPowSyncPrim->pui32LinAddr, RGXFWIF_DM_GP);
|
|
SyncPrimPDumpPol(psDevInfo->psPowSyncPrim,
|
1,
|
0xffffffff,
|
PDUMP_POLL_OPERATOR_EQUAL,
|
0);
|
#endif
|
|
return eError;
|
|
ErrorExit:
|
PVR_DPF((PVR_DBG_ERROR,"RGXCancelForcedIdleRequest: Firmware potentially left in forced idle state"));
|
return eError;
|
}
|
|
/*!
|
******************************************************************************
|
|
@Function PVRSRVGetNextDustCount
|
|
@Description
|
|
Calculate a sequence of dust counts to achieve full transition coverage.
|
We increment two counts of dusts and switch up and down between them.
|
It does contain a few redundant transitions. If two dust exist, the
|
output transitions should be as follows.
|
|
0->1, 0<-1, 0->2, 0<-2, (0->1)
|
1->1, 1->2, 1<-2, (1->2)
|
2->2, (2->0),
|
0->0. Repeat.
|
|
Redundant transitions in brackets.
|
|
@Input psDustReqState : Counter state used to calculate next dust count
|
@Input ui32DustCount : Number of dusts in the core
|
|
@Return PVRSRV_ERROR
|
|
******************************************************************************/
|
IMG_UINT32 RGXGetNextDustCount(RGX_DUST_STATE *psDustReqState, IMG_UINT32 ui32DustCount)
|
{
|
if (psDustReqState->bToggle)
|
{
|
psDustReqState->ui32DustCount2++;
|
}
|
|
if (psDustReqState->ui32DustCount2 > ui32DustCount)
|
{
|
psDustReqState->ui32DustCount1++;
|
psDustReqState->ui32DustCount2 = psDustReqState->ui32DustCount1;
|
}
|
|
if (psDustReqState->ui32DustCount1 > ui32DustCount)
|
{
|
psDustReqState->ui32DustCount1 = 0;
|
psDustReqState->ui32DustCount2 = 0;
|
}
|
|
psDustReqState->bToggle = !psDustReqState->bToggle;
|
|
return (psDustReqState->bToggle) ? psDustReqState->ui32DustCount1 : psDustReqState->ui32DustCount2;
|
}
|
|
/******************************************************************************
|
End of file (rgxpower.c)
|
******************************************************************************/
|
