/*************************************************************************/ /*!
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@File
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@Title Device specific initialisation routines
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Device specific MMU initialisation for the MIPS firmware
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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/* NB: this file is not to be included arbitrarily. It exists solely
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for the linkage between rgxinit.c and rgxmmuinit.c, the former
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being otherwise cluttered by the contents of the latter */
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#ifndef _SRVKM_RGXMIPSMMUINIT_H_
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#define _SRVKM_RGXMIPSMMUINIT_H_
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#include "device.h"
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#include "img_types.h"
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#include "mmu_common.h"
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#include "img_defs.h"
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/*
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Labelling of fields within virtual address. No PD and PC are used currently for
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the MIPS MMU
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*/
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/*
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Page Table entry #
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*/
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#define RGX_MIPS_MMUCTRL_VADDR_PT_INDEX_SHIFT (12U)
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#define RGX_MIPS_MMUCTRL_VADDR_PT_INDEX_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000FFF))
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/* PC entries related definitions */
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/* No PC is currently used for MIPS MMU */
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#define RGX_MIPS_MMUCTRL_PC_DATA_VALID_EN (0U)
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#define RGX_MIPS_MMUCTRL_PC_DATA_VALID_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PC_DATA_VALID_CLRMSK (0U)
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#define RGX_MIPS_MMUCTRL_PC_DATA_READ_ONLY_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PC_DATA_READ_ONLY_CLRMSK (0U)
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#define RGX_MIPS_MMUCTRL_PC_DATA_READ_ONLY_EN (0U)
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/* PD entries related definitions */
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/* No PD is currently used for MIPS MMU */
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#define RGX_MIPS_MMUCTRL_PD_DATA_VALID_EN (0U)
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#define RGX_MIPS_MMUCTRL_PD_DATA_VALID_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PD_DATA_VALID_CLRMSK (0U)
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#define RGX_MIPS_MMUCTRL_PD_DATA_READ_ONLY_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PD_DATA_READ_ONLY_CLRMSK (0U)
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#define RGX_MIPS_MMUCTRL_PD_DATA_READ_ONLY_EN (0U)
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/* PT entries related definitions */
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#define RGX_MIPS_MMUCTRL_PT_DATA_READ_INHIBIT_SHIFT (31U)
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#define RGX_MIPS_MMUCTRL_PT_DATA_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
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#define RGX_MIPS_MMUCTRL_PT_DATA_READ_INHIBIT_EN (0X80000000)
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#define RGX_MIPS_MMUCTRL_PT_DATA_WRITABLE_SHIFT (2U)
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#define RGX_MIPS_MMUCTRL_PT_DATA_WRITABLE_CLRMSK (0XFFFFFFFB)
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#define RGX_MIPS_MMUCTRL_PT_DATA_WRITABLE_EN (0X00000004)
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#define RGX_MIPS_MMUCTRL_PT_DATA_VALID_SHIFT (1U)
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#define RGX_MIPS_MMUCTRL_PT_DATA_VALID_CLRMSK (0XFFFFFFFD)
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#define RGX_MIPS_MMUCTRL_PT_DATA_VALID_EN (0X00000002)
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#define RGX_MIPS_MMUCTRL_PT_DATA_GLOBAL_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PT_DATA_GLOBAL_CLRMSK (0XFFFFFFFE)
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#define RGX_MIPS_MMUCTRL_PT_DATA_GLOBAL_EN (0X00000001)
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#define RGX_MIPS_MMUCTRL_PT_CACHE_POLICY_SHIFT (3U)
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#define RGX_MIPS_MMUCTRL_PT_CACHE_POLICY_CLRMSK (0XFFFFFFC7)
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/* "Uncached" caching policy*/
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#define RGX_MIPS_MMUCTRL_PT_UNCACHED_POLICY (0X00000007)
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/* "Write-back write-allocate" caching policy*/
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#define RGX_MIPS_MMUCTRL_PT_CACHED_POLICY (0X00000003)
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/* Physical page number inside MIPS MMU entries */
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#define RGX_MIPS_MMUCTRL_PT_PFN_SHIFT (6U)
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#define RGX_MIPS_MMUCTRL_PT_PFN_CLRMSK (0XFC00003F)
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/* Flags MIPS MMU entries */
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#define RGX_MIPS_MMUCTRL_PT_FLAGS_SHIFT (0U)
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#define RGX_MIPS_MMUCTRL_PT_FLAGS_CLRMSK (0XFFFFFFC0)
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IMG_EXPORT PVRSRV_ERROR RGXMipsMMUInit_Register(PVRSRV_DEVICE_NODE *psDeviceNode);
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IMG_EXPORT PVRSRV_ERROR RGXMipsMMUInit_Unregister(PVRSRV_DEVICE_NODE *psDeviceNode);
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#endif /* #ifndef _SRVKM_RGXMIPSMMUINIT_H_ */
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