/*************************************************************************/ /*!
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@File
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@Title DDK implementation of the Services abstraction layer
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description DDK implementation of the Services abstraction layer
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if defined (PDUMP)
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#include <stdarg.h>
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#endif
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#include "rgxlayer_km_impl.h"
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#include "pdump_km.h"
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#include "devicemem_utils.h"
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#include "pvrsrv.h"
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#include "rgxdevice.h"
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#include "rgxfwutils.h"
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void RGXWriteReg32(const void *hPrivate, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if( !(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW) )
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#endif
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{
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OSWriteHWReg32(pvRegsBase, ui32RegAddr, ui32RegValue);
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}
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PDUMPREG32(RGX_PDUMPREG_NAME, ui32RegAddr, ui32RegValue, psPowerParams->ui32PdumpFlags);
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}
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void RGXWriteReg64(const void *hPrivate, IMG_UINT32 ui32RegAddr, IMG_UINT64 ui64RegValue)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if( !(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW) )
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#endif
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{
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OSWriteHWReg64(pvRegsBase, ui32RegAddr, ui64RegValue);
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}
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PDUMPREG64(RGX_PDUMPREG_NAME, ui32RegAddr, ui64RegValue, psPowerParams->ui32PdumpFlags);
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}
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IMG_UINT32 RGXReadReg32(const void *hPrivate, IMG_UINT32 ui32RegAddr)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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IMG_UINT32 ui32RegValue;
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW)
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{
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ui32RegValue = IMG_UINT32_MAX;
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}
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else
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#endif
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{
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ui32RegValue = OSReadHWReg32(pvRegsBase, ui32RegAddr);
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}
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PDUMPREGREAD32(RGX_PDUMPREG_NAME, ui32RegAddr, psPowerParams->ui32PdumpFlags);
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return ui32RegValue;
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}
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IMG_UINT64 RGXReadReg64(const void *hPrivate, IMG_UINT32 ui32RegAddr)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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IMG_UINT64 ui64RegValue;
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW)
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{
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ui64RegValue = IMG_UINT64_MAX;
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}
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else
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#endif
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{
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ui64RegValue = OSReadHWReg64(pvRegsBase, ui32RegAddr);
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}
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PDUMPREGREAD64(RGX_PDUMPREG_NAME, ui32RegAddr, PDUMP_FLAGS_CONTINUOUS);
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return ui64RegValue;
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}
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PVRSRV_ERROR RGXPollReg32(const void *hPrivate,
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IMG_UINT32 ui32RegAddr,
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IMG_UINT32 ui32RegValue,
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IMG_UINT32 ui32RegMask)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if( !(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW) )
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#endif
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{
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if (PVRSRVPollForValueKM((IMG_UINT32 *)((IMG_UINT8*)pvRegsBase + ui32RegAddr),
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ui32RegValue,
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ui32RegMask) != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPollReg32: Poll for Reg (0x%x) failed", ui32RegAddr));
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return PVRSRV_ERROR_TIMEOUT;
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}
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}
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PDUMPREGPOL(RGX_PDUMPREG_NAME,
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ui32RegAddr,
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ui32RegValue,
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ui32RegMask,
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psPowerParams->ui32PdumpFlags,
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PDUMP_POLL_OPERATOR_EQUAL);
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return PVRSRV_OK;
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}
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PVRSRV_ERROR RGXPollReg64(const void *hPrivate,
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IMG_UINT32 ui32RegAddr,
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IMG_UINT64 ui64RegValue,
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IMG_UINT64 ui64RegMask)
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{
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RGX_POWER_LAYER_PARAMS *psPowerParams;
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PVRSRV_RGXDEV_INFO *psDevInfo;
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void *pvRegsBase;
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/* Split lower and upper words */
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IMG_UINT32 ui32UpperValue = (IMG_UINT32) (ui64RegValue >> 32);
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IMG_UINT32 ui32LowerValue = (IMG_UINT32) (ui64RegValue);
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IMG_UINT32 ui32UpperMask = (IMG_UINT32) (ui64RegMask >> 32);
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IMG_UINT32 ui32LowerMask = (IMG_UINT32) (ui64RegMask);
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PVR_ASSERT(hPrivate != NULL);
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psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
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psDevInfo = psPowerParams->psDevInfo;
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pvRegsBase = psDevInfo->pvRegsBaseKM;
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#if defined(PDUMP)
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if( !(psPowerParams->ui32PdumpFlags & PDUMP_FLAGS_NOHW) )
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#endif
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{
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if (PVRSRVPollForValueKM((IMG_UINT32 *)((IMG_UINT8*)pvRegsBase + ui32RegAddr + 4),
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ui32UpperValue,
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ui32UpperMask) != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPollReg64: Poll for upper part of Reg (0x%x) failed", ui32RegAddr));
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return PVRSRV_ERROR_TIMEOUT;
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}
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if (PVRSRVPollForValueKM((IMG_UINT32 *)((IMG_UINT8*)pvRegsBase + ui32RegAddr),
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ui32LowerValue,
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ui32LowerMask) != PVRSRV_OK)
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{
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PVR_DPF((PVR_DBG_ERROR, "RGXPollReg64: Poll for upper part of Reg (0x%x) failed", ui32RegAddr));
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return PVRSRV_ERROR_TIMEOUT;
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}
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}
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PDUMPREGPOL(RGX_PDUMPREG_NAME,
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ui32RegAddr + 4,
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ui32UpperValue,
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ui32UpperMask,
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psPowerParams->ui32PdumpFlags,
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PDUMP_POLL_OPERATOR_EQUAL);
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PDUMPREGPOL(RGX_PDUMPREG_NAME,
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ui32RegAddr,
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ui32LowerValue,
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ui32LowerMask,
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psPowerParams->ui32PdumpFlags,
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PDUMP_POLL_OPERATOR_EQUAL);
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return PVRSRV_OK;
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}
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void RGXWaitCycles(const void *hPrivate, IMG_UINT32 ui32Cycles, IMG_UINT32 ui32TimeUs)
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{
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PVR_UNREFERENCED_PARAMETER(hPrivate);
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OSWaitus(ui32TimeUs);
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PDUMPIDLWITHFLAGS(ui32Cycles, PDUMP_FLAGS_CONTINUOUS);
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}
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void RGXCommentLogPower(const void *hPrivate, const IMG_CHAR *pszString, ...)
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{
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#if defined(PDUMP)
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va_list argList;
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va_start(argList, pszString);
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PDumpCommentWithFlagsVA(PDUMP_FLAGS_CONTINUOUS, pszString, argList);
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va_end(argList);
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PVR_UNREFERENCED_PARAMETER(hPrivate);
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#else
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PVR_UNREFERENCED_PARAMETER(hPrivate);
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PVR_UNREFERENCED_PARAMETER(pszString);
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#endif
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}
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void RGXAcquireKernelMMUPC(const void *hPrivate, IMG_DEV_PHYADDR *psPCAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psPCAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sPCAddr;
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}
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#if defined(PDUMP)
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void RGXWriteKernelMMUPC64(const void *hPrivate,
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IMG_UINT32 ui32PCReg,
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IMG_UINT32 ui32PCRegAlignShift,
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IMG_UINT32 ui32PCRegShift,
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IMG_UINT64 ui64PCVal)
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{
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PVRSRV_RGXDEV_INFO *psDevInfo;
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PVR_ASSERT(hPrivate != NULL);
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psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
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/* Write the cat-base address */
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OSWriteHWReg64(psDevInfo->pvRegsBaseKM, ui32PCReg, ui64PCVal);
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/* Pdump catbase address */
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MMU_PDumpWritePageCatBase(psDevInfo->psKernelMMUCtx,
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RGX_PDUMPREG_NAME,
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ui32PCReg,
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8,
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ui32PCRegAlignShift,
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ui32PCRegShift,
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PDUMP_FLAGS_CONTINUOUS);
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}
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void RGXWriteKernelMMUPC32(const void *hPrivate,
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IMG_UINT32 ui32PCReg,
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IMG_UINT32 ui32PCRegAlignShift,
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IMG_UINT32 ui32PCRegShift,
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IMG_UINT32 ui32PCVal)
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{
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PVRSRV_RGXDEV_INFO *psDevInfo;
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PVR_ASSERT(hPrivate != NULL);
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psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
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/* Write the cat-base address */
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OSWriteHWReg32(psDevInfo->pvRegsBaseKM, ui32PCReg, ui32PCVal);
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/* Pdump catbase address */
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MMU_PDumpWritePageCatBase(psDevInfo->psKernelMMUCtx,
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RGX_PDUMPREG_NAME,
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ui32PCReg,
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4,
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ui32PCRegAlignShift,
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ui32PCRegShift,
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PDUMP_FLAGS_CONTINUOUS);
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}
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#endif /* defined(PDUMP) */
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void RGXAcquireGPURegsAddr(const void *hPrivate, IMG_DEV_PHYADDR *psGPURegsAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psGPURegsAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sGPURegAddr;
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}
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#if defined(PDUMP)
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void RGXMIPSWrapperConfig(const void *hPrivate,
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IMG_UINT32 ui32RegAddr,
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IMG_UINT64 ui64GPURegsAddr,
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IMG_UINT32 ui32GPURegsAlign,
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IMG_UINT32 ui32BootMode)
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{
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PVRSRV_RGXDEV_INFO *psDevInfo;
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PVR_ASSERT(hPrivate != NULL);
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psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
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OSWriteHWReg64(psDevInfo->pvRegsBaseKM,
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ui32RegAddr,
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(ui64GPURegsAddr >> ui32GPURegsAlign) | ui32BootMode);
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/* Store register offset to temp PDump variable */
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PDumpRegLabelToInternalVar(RGX_PDUMPREG_NAME, ui32RegAddr, ":SYSMEM:$1", PDUMP_FLAGS_CONTINUOUS);
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/* Align register transactions identifier */
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PDumpWriteVarSHRValueOp(":SYSMEM:$1", ui32GPURegsAlign, PDUMP_FLAGS_CONTINUOUS);
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/* Enable micromips instruction encoding */
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PDumpWriteVarORValueOp(":SYSMEM:$1", ui32BootMode, PDUMP_FLAGS_CONTINUOUS);
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/* Do the actual register write */
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PDumpInternalVarToReg64(RGX_PDUMPREG_NAME, ui32RegAddr, ":SYSMEM:$1", 0);
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}
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#endif
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void RGXAcquireBootRemapAddr(const void *hPrivate, IMG_DEV_PHYADDR *psBootRemapAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psBootRemapAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sBootRemapAddr;
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}
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void RGXAcquireCodeRemapAddr(const void *hPrivate, IMG_DEV_PHYADDR *psCodeRemapAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psCodeRemapAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sCodeRemapAddr;
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}
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void RGXAcquireDataRemapAddr(const void *hPrivate, IMG_DEV_PHYADDR *psDataRemapAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psDataRemapAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sDataRemapAddr;
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}
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void RGXAcquireTrampolineRemapAddr(const void *hPrivate, IMG_DEV_PHYADDR *psTrampolineRemapAddr)
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{
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PVR_ASSERT(hPrivate != NULL);
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*psTrampolineRemapAddr = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->sTrampolineRemapAddr;
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}
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#if defined(PDUMP)
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static inline
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void RGXWriteRemapConfig2Reg(void *pvRegs,
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PMR *psPMR,
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IMG_DEVMEM_OFFSET_T uiLogicalOffset,
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IMG_UINT32 ui32RegAddr,
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IMG_UINT64 ui64PhyAddr,
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IMG_UINT64 ui64PhyMask,
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IMG_UINT64 ui64Settings)
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{
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OSWriteHWReg64(pvRegs, ui32RegAddr, (ui64PhyAddr & ui64PhyMask) | ui64Settings);
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/* Store memory offset to temp PDump variable */
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PDumpMemLabelToInternalVar(":SYSMEM:$1", psPMR, uiLogicalOffset, PDUMP_FLAGS_CONTINUOUS);
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/* Keep only the relevant bits of the output physical address */
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PDumpWriteVarANDValueOp(":SYSMEM:$1", ui64PhyMask, PDUMP_FLAGS_CONTINUOUS);
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/* Extra settings for this remapped region */
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PDumpWriteVarORValueOp(":SYSMEM:$1", ui64Settings, PDUMP_FLAGS_CONTINUOUS);
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/* Do the actual register write */
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PDumpInternalVarToReg32(RGX_PDUMPREG_NAME, ui32RegAddr, ":SYSMEM:$1", PDUMP_FLAGS_CONTINUOUS);
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}
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void RGXBootRemapConfig(const void *hPrivate,
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IMG_UINT32 ui32Config1RegAddr,
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IMG_UINT64 ui64Config1RegValue,
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IMG_UINT32 ui32Config2RegAddr,
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IMG_UINT64 ui64Config2PhyAddr,
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IMG_UINT64 ui64Config2PhyMask,
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IMG_UINT64 ui64Config2Settings)
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{
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PVRSRV_RGXDEV_INFO *psDevInfo;
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IMG_UINT32 ui32BootRemapMemOffset = RGXMIPSFW_BOOT_NMI_CODE_BASE_PAGE * (IMG_UINT32)RGXMIPSFW_PAGE_SIZE;
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PVR_ASSERT(hPrivate != NULL);
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psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
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/* Write remap config1 register */
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RGXWriteReg64(hPrivate,
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ui32Config1RegAddr,
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ui64Config1RegValue);
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/* Write remap config2 register */
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RGXWriteRemapConfig2Reg(psDevInfo->pvRegsBaseKM,
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psDevInfo->psRGXFWCodeMemDesc->psImport->hPMR,
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psDevInfo->psRGXFWCodeMemDesc->uiOffset + ui32BootRemapMemOffset,
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ui32Config2RegAddr,
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ui64Config2PhyAddr,
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ui64Config2PhyMask,
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ui64Config2Settings);
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}
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void RGXCodeRemapConfig(const void *hPrivate,
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IMG_UINT32 ui32Config1RegAddr,
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IMG_UINT64 ui64Config1RegValue,
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IMG_UINT32 ui32Config2RegAddr,
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IMG_UINT64 ui64Config2PhyAddr,
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IMG_UINT64 ui64Config2PhyMask,
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IMG_UINT64 ui64Config2Settings)
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{
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PVRSRV_RGXDEV_INFO *psDevInfo;
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IMG_UINT32 ui32CodeRemapMemOffset = RGXMIPSFW_EXCEPTIONSVECTORS_BASE_PAGE * (IMG_UINT32)RGXMIPSFW_PAGE_SIZE;
|
|
PVR_ASSERT(hPrivate != NULL);
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psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
|
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/* Write remap config1 register */
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RGXWriteReg64(hPrivate,
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ui32Config1RegAddr,
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ui64Config1RegValue);
|
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/* Write remap config2 register */
|
RGXWriteRemapConfig2Reg(psDevInfo->pvRegsBaseKM,
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psDevInfo->psRGXFWCodeMemDesc->psImport->hPMR,
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psDevInfo->psRGXFWCodeMemDesc->uiOffset + ui32CodeRemapMemOffset,
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ui32Config2RegAddr,
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ui64Config2PhyAddr,
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ui64Config2PhyMask,
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ui64Config2Settings);
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}
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void RGXDataRemapConfig(const void *hPrivate,
|
IMG_UINT32 ui32Config1RegAddr,
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IMG_UINT64 ui64Config1RegValue,
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IMG_UINT32 ui32Config2RegAddr,
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IMG_UINT64 ui64Config2PhyAddr,
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IMG_UINT64 ui64Config2PhyMask,
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IMG_UINT64 ui64Config2Settings)
|
{
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
IMG_UINT32 ui32DataRemapMemOffset = RGXMIPSFW_BOOT_NMI_DATA_BASE_PAGE * (IMG_UINT32)RGXMIPSFW_PAGE_SIZE;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
|
|
/* Write remap config1 register */
|
RGXWriteReg64(hPrivate,
|
ui32Config1RegAddr,
|
ui64Config1RegValue);
|
|
/* Write remap config2 register */
|
RGXWriteRemapConfig2Reg(psDevInfo->pvRegsBaseKM,
|
psDevInfo->psRGXFWDataMemDesc->psImport->hPMR,
|
psDevInfo->psRGXFWDataMemDesc->uiOffset + ui32DataRemapMemOffset,
|
ui32Config2RegAddr,
|
ui64Config2PhyAddr,
|
ui64Config2PhyMask,
|
ui64Config2Settings);
|
}
|
#endif
|
|
|
|
#define MAX_NUM_COHERENCY_TESTS (10)
|
IMG_BOOL RGXDoFWSlaveBoot(const void *hPrivate)
|
{
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
PVRSRV_DEVICE_CONFIG *psDevConfig;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
|
|
if (psDevInfo->ui32CoherencyTestsDone >= MAX_NUM_COHERENCY_TESTS)
|
{
|
return IMG_FALSE;
|
}
|
|
psDevConfig = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevConfig;
|
|
return PVRSRVSystemSnoopingOfCPUCache(psDevConfig);
|
}
|
|
PVRSRV_ERROR RGXIOCoherencyTest(const void *hPrivate)
|
{
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
DEVMEM_MEMDESC *psIOCoherencyTestMemDesc;
|
IMG_UINT32 *pui32CpuVirtAddr;
|
RGXFWIF_DEV_VIRTADDR sCoherencyTestBuffer;
|
IMG_DEVMEM_SIZE_T uiCoherencyBlockSize = sizeof(IMG_UINT64);
|
IMG_DEVMEM_ALIGN_T uiCoherencyBlockAlign = sizeof(IMG_UINT64);
|
IMG_UINT32 ui32SLCCTRL;
|
IMG_UINT32 ui32TestNum;
|
PVRSRV_ERROR eError = PVRSRV_OK;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psDevInfo = ((RGX_POWER_LAYER_PARAMS*)hPrivate)->psDevInfo;
|
|
/* Size and align are 'expanded' because we request an export align allocation */
|
DevmemExportalignAdjustSizeAndAlign(DevmemGetHeapLog2PageSize(psDevInfo->psFirmwareHeap),
|
&uiCoherencyBlockSize,
|
&uiCoherencyBlockAlign);
|
|
/* Allocate, acquire cpu address and set firmware address */
|
eError = DevmemFwAllocateExportable(psDevInfo->psDeviceNode,
|
uiCoherencyBlockSize,
|
uiCoherencyBlockAlign,
|
PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(PMMETA_PROTECT) |
|
PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE |
|
PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC |
|
PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT |
|
PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT |
|
PVRSRV_MEMALLOCFLAG_GPU_READABLE |
|
PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE |
|
PVRSRV_MEMALLOCFLAG_CPU_READABLE |
|
PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE,
|
"FwExIoCoherencyTestBuffer",
|
&psIOCoherencyTestMemDesc);
|
PVR_ASSERT(eError == PVRSRV_OK);
|
|
eError = DevmemAcquireCpuVirtAddr(psIOCoherencyTestMemDesc,
|
(void **) &pui32CpuVirtAddr);
|
PVR_ASSERT(eError == PVRSRV_OK);
|
|
/* Create a FW address which is uncached in the Meta DCache and in the SLC
|
* using the Meta bootloader segment.
|
* This segment is the only one configured correctly out of reset
|
* (when this test is meant to be executed).
|
*/
|
{
|
RGXSetFirmwareAddress(&sCoherencyTestBuffer,
|
psIOCoherencyTestMemDesc,
|
0,
|
RFW_FWADDR_FLAG_NONE);
|
|
/* Undo most of the FW mappings done by RGXSetFirmwareAddress */
|
sCoherencyTestBuffer.ui32Addr &= ~RGXFW_SEGMMU_DATA_META_CACHE_MASK;
|
sCoherencyTestBuffer.ui32Addr &= ~RGXFW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK;
|
sCoherencyTestBuffer.ui32Addr -= RGXFW_SEGMMU_DATA_BASE_ADDRESS;
|
|
/* Map the buffer in the bootloader segment as uncached */
|
sCoherencyTestBuffer.ui32Addr |= RGXFW_BOOTLDR_META_ADDR;
|
sCoherencyTestBuffer.ui32Addr |= RGXFW_SEGMMU_DATA_META_UNCACHED;
|
}
|
|
/* Bypass the SLC when IO coherency is enabled */
|
ui32SLCCTRL = RGXReadReg32(hPrivate, RGX_CR_SLC_CTRL_BYPASS);
|
RGXWriteReg32(hPrivate,
|
RGX_CR_SLC_CTRL_BYPASS,
|
ui32SLCCTRL | RGX_CR_SLC_CTRL_BYPASS_BYP_CC_EN);
|
|
for (ui32TestNum = 1; ui32TestNum < 3; ui32TestNum++)
|
{
|
IMG_UINT32 i;
|
IMG_BOOL bPassed = IMG_TRUE;
|
|
PVR_LOG(("Startup I/O Coherency Test [pass #%u]", ui32TestNum));
|
|
for (i = 0; i < uiCoherencyBlockSize/sizeof(IMG_UINT32); i++)
|
{
|
IMG_UINT32 ui32FWAddr, ui32FWValue;
|
PVRSRV_ERROR eError2;
|
|
/* Ensures line is in dcache */
|
ui32FWValue = pui32CpuVirtAddr[i];
|
|
/* Dirty allocation in dcache */
|
pui32CpuVirtAddr[i] = i + ui32TestNum;
|
|
/* Flush possible cpu store-buffer(ing) */
|
OSWriteMemoryBarrier();
|
|
/* Read back value using RGX slave-port interface */
|
ui32FWAddr = sCoherencyTestBuffer.ui32Addr + (i * sizeof(IMG_UINT32));
|
|
eError2 = RGXReadMETAAddr(psDevInfo, ui32FWAddr, &ui32FWValue);
|
|
if (eError2 != PVRSRV_OK)
|
{
|
PVR_DPF((PVR_DBG_ERROR, "RGXReadWithSP error: %s",
|
PVRSRVGetErrorStringKM(eError2)));
|
}
|
|
/* Compare to see if I/O coherency worked */
|
if (pui32CpuVirtAddr[i] != ui32FWValue)
|
{
|
PVR_DPF((PVR_DBG_ERROR, "Expected: %x, Got: %x",
|
pui32CpuVirtAddr[i], ui32FWValue));
|
|
bPassed = IMG_FALSE;
|
eError = PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
|
PVR_LOG(("I/O Coherency Test [pass #%u] completed, Passed? %d",
|
ui32TestNum, bPassed));
|
}
|
|
/* Restore SLC bypass settings */
|
RGXWriteReg32(hPrivate, RGX_CR_SLC_CTRL_BYPASS, ui32SLCCTRL);
|
|
RGXUnsetFirmwareAddress(psIOCoherencyTestMemDesc);
|
DevmemReleaseCpuVirtAddr(psIOCoherencyTestMemDesc);
|
DevmemFwFree(psDevInfo, psIOCoherencyTestMemDesc);
|
|
if (eError == PVRSRV_OK)
|
{
|
PVR_LOG(("I/O Coherency Test succeeded"));
|
psDevInfo->ui32CoherencyTestsDone = MAX_NUM_COHERENCY_TESTS + 1;
|
}
|
else
|
{
|
PVR_LOG(("I/O Coherency Test FAILED"));
|
psDevInfo->ui32CoherencyTestsDone++;
|
}
|
|
return eError;
|
}
|
|
IMG_BOOL RGXDeviceHasFeaturePower(const void *hPrivate, IMG_UINT64 ui64Feature)
|
{
|
RGX_POWER_LAYER_PARAMS *psPowerParams;
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
|
psDevInfo = psPowerParams->psDevInfo;
|
|
return (psDevInfo->sDevFeatureCfg.ui64Features & ui64Feature) != 0;
|
}
|
|
IMG_BOOL RGXDeviceHasErnBrnPower(const void *hPrivate, IMG_UINT64 ui64ErnsBrns)
|
{
|
RGX_POWER_LAYER_PARAMS *psPowerParams;
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
|
psDevInfo = psPowerParams->psDevInfo;
|
|
return (psDevInfo->sDevFeatureCfg.ui64ErnsBrns & ui64ErnsBrns) != 0;
|
}
|
|
IMG_UINT32 RGXGetDeviceSLCBanks(const void *hPrivate)
|
{
|
RGX_POWER_LAYER_PARAMS *psPowerParams;
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
|
psDevInfo = psPowerParams->psDevInfo;
|
|
return psDevInfo->sDevFeatureCfg.ui32SLCBanks;
|
}
|
|
IMG_UINT32 RGXGetDeviceSLCSize(const void *hPrivate)
|
{
|
RGX_POWER_LAYER_PARAMS *psPowerParams;
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
|
psDevInfo = psPowerParams->psDevInfo;
|
|
return psDevInfo->sDevFeatureCfg.ui32SLCSize;
|
}
|
|
IMG_UINT32 RGXGetDeviceCacheLineSize(const void *hPrivate)
|
{
|
RGX_POWER_LAYER_PARAMS *psPowerParams;
|
PVRSRV_RGXDEV_INFO *psDevInfo;
|
|
PVR_ASSERT(hPrivate != NULL);
|
psPowerParams = (RGX_POWER_LAYER_PARAMS*)hPrivate;
|
psDevInfo = psPowerParams->psDevInfo;
|
|
return psDevInfo->sDevFeatureCfg.ui32CacheLineSize;
|
}
|
