/*************************************************************************/ /*!
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@File
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@Title Services Firmware image utilities used at init time
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Services Firmware image utilities used at init time
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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/* The routines implemented here are built on top of an abstraction layer to
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* hide DDK/OS-specific details in case they are used outside of the DDK
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* (e.g. when trusted device is enabled).
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* Any new dependency should be added to rgxlayer.h.
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* Any new code should be built on top of the existing abstraction layer,
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* which should be extended when necessary. */
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#include "rgxfwimageutils.h"
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|
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/************************************************************************
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* FW Segments configuration
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************************************************************************/
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typedef struct _RGX_FW_SEGMENT_
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{
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IMG_UINT32 ui32SegId; /*!< Segment Id */
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IMG_UINT32 ui32SegStartAddr; /*!< Segment Start Addr */
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IMG_UINT32 ui32SegAllocSize; /*!< Amount of memory to allocate for that segment */
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IMG_UINT32 ui32FWMemOffset; /*!< Offset of this segment in the collated FW mem allocation */
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const IMG_CHAR *pszSegName;
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} RGX_FW_SEGMENT;
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typedef struct _RGX_FW_SEGMENT_LIST_
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{
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RGX_FW_SEGMENT *psRGXFWCodeSeg;
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RGX_FW_SEGMENT *psRGXFWDataSeg;
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IMG_UINT32 ui32CodeSegCount;
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IMG_UINT32 ui32DataSegCount;
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} RGX_FW_SEGMENT_LIST;
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|
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#if defined(RGX_FEATURE_META) || defined(SUPPORT_KERNEL_SRVINIT)
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static RGX_FW_SEGMENT asRGXMetaFWCodeSegments[] = {
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/* Seg ID Seg Start Addr Alloc size FWMem offset Name */
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{RGXFW_SEGMMU_TEXT_ID, RGXFW_BOOTLDR_META_ADDR, 0x31000, 0, "Bootldr and Code"}, /* Has to be the first one to get the proper DevV addr */
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};
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static RGX_FW_SEGMENT asRGXMetaFWDataSegments[] = {
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/* Seg ID Seg Start Addr Alloc size FWMem offset Name */
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{RGXFW_SEGMMU_DATA_ID, 0x38880000, 0x17000, 0, "Local Shared and Data"},
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};
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#define RGXFW_META_NUM_CODE_SEGMENTS (sizeof(asRGXMetaFWCodeSegments)/sizeof(asRGXMetaFWCodeSegments[0]))
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#define RGXFW_META_NUM_DATA_SEGMENTS (sizeof(asRGXMetaFWDataSegments)/sizeof(asRGXMetaFWDataSegments[0]))
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#endif
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#if defined(RGX_FEATURE_MIPS) || defined(SUPPORT_KERNEL_SRVINIT)
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static RGX_FW_SEGMENT asRGXMipsFWCodeSegments[] = {
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/* Seg ID Seg Start Addr Alloc size FWMem offset Name */
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{ 0, RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE, RGXMIPSFW_BOOT_NMI_CODE_SIZE, RGXMIPSFW_BOOT_NMI_CODE_OFFSET, "Bootldr and NMI code"},
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{ 1, RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE, RGXMIPSFW_EXCEPTIONSVECTORS_SIZE, RGXMIPSFW_EXCEPTIONSVECTORS_OFFSET, "Exception vectors"},
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{ 2, RGXMIPSFW_CODE_VIRTUAL_BASE, RGXMIPSFW_CODE_SIZE, RGXMIPSFW_CODE_OFFSET, "Text"},
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};
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static RGX_FW_SEGMENT asRGXMipsFWDataSegments[] = {
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/* Seg ID Seg Start Addr Alloc size FWMem offset Name */
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{ 3, RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE, RGXMIPSFW_BOOT_NMI_DATA_SIZE, RGXMIPSFW_BOOT_NMI_DATA_OFFSET, "Bootldr and NMI data"},
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{ 4, RGXMIPSFW_DATA_VIRTUAL_BASE, RGXMIPSFW_DATA_SIZE, RGXMIPSFW_DATA_OFFSET, "Local Data"},
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{ 5, RGXMIPSFW_STACK_VIRTUAL_BASE, RGXMIPSFW_STACK_SIZE, RGXMIPSFW_DATA_SIZE, "Stack"},
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};
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#define RGXFW_MIPS_NUM_CODE_SEGMENTS (sizeof(asRGXMipsFWCodeSegments)/sizeof(asRGXMipsFWCodeSegments[0]))
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#define RGXFW_MIPS_NUM_DATA_SEGMENTS (sizeof(asRGXMipsFWDataSegments)/sizeof(asRGXMipsFWDataSegments[0]))
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#endif
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/*!
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*******************************************************************************
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@Function FindMMUSegment
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@Description Given a 32 bit FW address attempt to find the corresponding
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pointer to FW allocation
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@Input ui32OffsetIn : 32 bit FW address
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@Input pvHostFWCodeAddr : Pointer to FW code
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@Input pvHostFWDataAddr : Pointer to FW data
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@Input uiHostAddrOut : CPU pointer equivalent to ui32OffsetIn
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@Return PVRSRV_ERROR
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******************************************************************************/
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static PVRSRV_ERROR FindMMUSegment(IMG_UINT32 ui32OffsetIn,
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void *pvHostFWCodeAddr,
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void *pvHostFWDataAddr,
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void **uiHostAddrOut,
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RGX_FW_SEGMENT_LIST *psRGXFWSegList)
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{
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RGX_FW_SEGMENT *psSegArr;
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IMG_UINT32 i;
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psSegArr = psRGXFWSegList->psRGXFWCodeSeg;
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for (i = 0; i < psRGXFWSegList->ui32CodeSegCount; i++)
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{
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if ((ui32OffsetIn >= psSegArr[i].ui32SegStartAddr) &&
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(ui32OffsetIn < (psSegArr[i].ui32SegStartAddr + psSegArr[i].ui32SegAllocSize)))
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{
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*uiHostAddrOut = pvHostFWCodeAddr;
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goto found;
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}
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}
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psSegArr = psRGXFWSegList->psRGXFWDataSeg;
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for (i = 0; i < psRGXFWSegList->ui32DataSegCount; i++)
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{
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if ((ui32OffsetIn >= psSegArr[i].ui32SegStartAddr) &&
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(ui32OffsetIn < (psSegArr[i].ui32SegStartAddr + psSegArr[i].ui32SegAllocSize)))
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{
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*uiHostAddrOut = pvHostFWDataAddr;
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goto found;
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}
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}
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return PVRSRV_ERROR_INIT_FAILURE;
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found:
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/* Direct Mem write to mapped memory */
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ui32OffsetIn -= psSegArr[i].ui32SegStartAddr;
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ui32OffsetIn += psSegArr[i].ui32FWMemOffset;
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/* Add offset to pointer to FW allocation only if
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* that allocation is available
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*/
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if (*uiHostAddrOut)
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{
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*(IMG_UINT8 **)uiHostAddrOut += ui32OffsetIn;
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}
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return PVRSRV_OK;
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}
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#if defined(RGX_FEATURE_META) || defined(SUPPORT_KERNEL_SRVINIT)
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/*!
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*******************************************************************************
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@Function RGXFWConfigureSegID
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@Description Configures a single segment of the Segment MMU
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(base, limit and out_addr)
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@Input hPrivate : Implementation specific data
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@Input ui64SegOutAddr : Segment output base address (40 bit devVaddr)
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@Input ui32SegBase : Segment input base address (32 bit FW address)
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@Input ui32SegLimit : Segment size
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@Input ui32SegID : Segment ID
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@Input pszName : Segment name
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@Input ppui32BootConf : Pointer to bootloader data
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@Return void
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******************************************************************************/
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static void RGXFWConfigureSegID(const void *hPrivate,
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IMG_UINT64 ui64SegOutAddr,
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IMG_UINT32 ui32SegBase,
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IMG_UINT32 ui32SegLimit,
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IMG_UINT32 ui32SegID,
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const IMG_CHAR *pszName,
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IMG_UINT32 **ppui32BootConf)
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{
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IMG_UINT32 *pui32BootConf = *ppui32BootConf;
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IMG_UINT32 ui32SegOutAddr0 = ui64SegOutAddr & 0x00000000FFFFFFFFUL;
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IMG_UINT32 ui32SegOutAddr1 = (ui64SegOutAddr >> 32) & 0x00000000FFFFFFFFUL;
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/* META segments have a minimum size */
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IMG_UINT32 ui32LimitOff = (ui32SegLimit < RGXFW_SEGMMU_ALIGN) ?
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RGXFW_SEGMMU_ALIGN : ui32SegLimit;
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/* the limit is an offset, therefore off = size - 1 */
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ui32LimitOff -= 1;
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RGXCommentLogInit(hPrivate,
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"* FW %s - seg%d: meta_addr = 0x%08x, devv_addr = 0x%llx, limit = 0x%x",
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pszName, ui32SegID,
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ui32SegBase, (unsigned long long)ui64SegOutAddr,
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ui32LimitOff);
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ui32SegBase |= RGXFW_SEGMMU_ALLTHRS_WRITEABLE;
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*pui32BootConf++ = META_CR_MMCU_SEGMENTn_BASE(ui32SegID);
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*pui32BootConf++ = ui32SegBase;
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*pui32BootConf++ = META_CR_MMCU_SEGMENTn_LIMIT(ui32SegID);
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*pui32BootConf++ = ui32LimitOff;
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*pui32BootConf++ = META_CR_MMCU_SEGMENTn_OUTA0(ui32SegID);
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*pui32BootConf++ = ui32SegOutAddr0;
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*pui32BootConf++ = META_CR_MMCU_SEGMENTn_OUTA1(ui32SegID);
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*pui32BootConf++ = ui32SegOutAddr1;
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*ppui32BootConf = pui32BootConf;
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}
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/*!
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*******************************************************************************
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@Function RGXFWConfigureSegMMU
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@Description Configures META's Segment MMU
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@Input hPrivate : Implementation specific data
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@Input psFWCodeDevVAddrBase : FW code base device virtual address
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@Input psFWDataDevVAddrBase : FW data base device virtual address
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@Input ppui32BootConf : Pointer to bootloader data
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@Return void
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******************************************************************************/
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static void RGXFWConfigureSegMMU(const void *hPrivate,
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IMG_DEV_VIRTADDR *psFWCodeDevVAddrBase,
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IMG_DEV_VIRTADDR *psFWDataDevVAddrBase,
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IMG_UINT32 **ppui32BootConf)
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{
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IMG_UINT64 ui64SegOutAddr;
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IMG_UINT32 i;
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PVR_UNREFERENCED_PARAMETER(psFWCodeDevVAddrBase);
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/* Configure Segment MMU */
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RGXCommentLogInit(hPrivate, "********** FW configure Segment MMU **********");
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for (i = 0; i < RGXFW_META_NUM_DATA_SEGMENTS ; i++)
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{
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ui64SegOutAddr = (psFWDataDevVAddrBase->uiAddr |
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RGXFW_SEGMMU_OUTADDR_TOP(META_MMU_CONTEXT_MAPPING, RGXFW_SEGMMU_META_DM_ID)) +
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asRGXMetaFWDataSegments[i].ui32FWMemOffset;
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RGXFWConfigureSegID(hPrivate,
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ui64SegOutAddr,
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asRGXMetaFWDataSegments[i].ui32SegStartAddr,
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asRGXMetaFWDataSegments[i].ui32SegAllocSize,
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asRGXMetaFWDataSegments[i].ui32SegId,
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asRGXMetaFWDataSegments[i].pszSegName,
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ppui32BootConf); /*write the sequence to the bootldr */
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}
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}
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/*!
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*******************************************************************************
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@Function RGXFWConfigureMetaCaches
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@Description Configure and enable the Meta instruction and data caches
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@Input hPrivate : Implementation specific data
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@Input ui32NumThreads : Number of FW threads in use
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@Input ui32MainThreadID : ID of the FW thread in use
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(only meaningful if ui32NumThreads == 1)
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@Input ppui32BootConf : Pointer to bootloader data
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@Return void
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******************************************************************************/
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static void RGXFWConfigureMetaCaches(const void *hPrivate,
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IMG_UINT32 ui32NumThreads,
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IMG_UINT32 ui32MainThreadID,
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IMG_UINT32 **ppui32BootConf)
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{
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IMG_UINT32 *pui32BootConf = *ppui32BootConf;
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IMG_UINT32 ui32DCacheT0, ui32ICacheT0;
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IMG_UINT32 ui32DCacheT1, ui32ICacheT1;
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IMG_UINT32 ui32DCacheT2, ui32ICacheT2;
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IMG_UINT32 ui32DCacheT3, ui32ICacheT3;
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#define META_CR_MMCU_LOCAL_EBCTRL (0x04830600)
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#define META_CR_MMCU_LOCAL_EBCTRL_ICWIN (0x3 << 14)
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#define META_CR_MMCU_LOCAL_EBCTRL_DCWIN (0x3 << 6)
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#define META_CR_SYSC_DCPART(n) (0x04830200 + (n)*0x8)
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#define META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE (0x1 << 31)
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#define META_CR_SYSC_ICPART(n) (0x04830220 + (n)*0x8)
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#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF (0x8 << 16)
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#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE (0xF)
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#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE (0x7)
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#define META_CR_MMCU_DCACHE_CTRL (0x04830018)
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#define META_CR_MMCU_ICACHE_CTRL (0x04830020)
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#define META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN (0x1)
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|
RGXCommentLogInit(hPrivate, "********** Meta caches configuration *********");
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|
/* Initialise I/Dcache settings */
|
ui32DCacheT0 = ui32DCacheT1 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
|
ui32DCacheT2 = ui32DCacheT3 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
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ui32ICacheT0 = ui32ICacheT1 = ui32ICacheT2 = ui32ICacheT3 = 0;
|
|
if (ui32NumThreads == 1)
|
{
|
if (ui32MainThreadID == 0)
|
{
|
ui32DCacheT0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
ui32ICacheT0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
}
|
else
|
{
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ui32DCacheT1 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
ui32ICacheT1 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
}
|
}
|
else
|
{
|
ui32DCacheT0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE;
|
ui32ICacheT0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE;
|
|
ui32DCacheT1 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE |
|
META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF;
|
ui32ICacheT1 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE |
|
META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF;
|
}
|
|
/* Local region MMU enhanced bypass: WIN-3 mode for code and data caches */
|
*pui32BootConf++ = META_CR_MMCU_LOCAL_EBCTRL;
|
*pui32BootConf++ = META_CR_MMCU_LOCAL_EBCTRL_ICWIN |
|
META_CR_MMCU_LOCAL_EBCTRL_DCWIN;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_MMCU_LOCAL_EBCTRL,
|
META_CR_MMCU_LOCAL_EBCTRL_ICWIN | META_CR_MMCU_LOCAL_EBCTRL_DCWIN);
|
|
/* Data cache partitioning thread 0 to 3 */
|
*pui32BootConf++ = META_CR_SYSC_DCPART(0);
|
*pui32BootConf++ = ui32DCacheT0;
|
*pui32BootConf++ = META_CR_SYSC_DCPART(1);
|
*pui32BootConf++ = ui32DCacheT1;
|
*pui32BootConf++ = META_CR_SYSC_DCPART(2);
|
*pui32BootConf++ = ui32DCacheT2;
|
*pui32BootConf++ = META_CR_SYSC_DCPART(3);
|
*pui32BootConf++ = ui32DCacheT3;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_DCPART(0), ui32DCacheT0);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_DCPART(1), ui32DCacheT1);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_DCPART(2), ui32DCacheT2);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_DCPART(3), ui32DCacheT3);
|
|
/* Enable data cache hits */
|
*pui32BootConf++ = META_CR_MMCU_DCACHE_CTRL;
|
*pui32BootConf++ = META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_MMCU_DCACHE_CTRL,
|
META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
|
|
/* Instruction cache partitioning thread 0 to 3 */
|
*pui32BootConf++ = META_CR_SYSC_ICPART(0);
|
*pui32BootConf++ = ui32ICacheT0;
|
*pui32BootConf++ = META_CR_SYSC_ICPART(1);
|
*pui32BootConf++ = ui32ICacheT1;
|
*pui32BootConf++ = META_CR_SYSC_ICPART(2);
|
*pui32BootConf++ = ui32ICacheT2;
|
*pui32BootConf++ = META_CR_SYSC_ICPART(3);
|
*pui32BootConf++ = ui32ICacheT3;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_ICPART(0), ui32ICacheT0);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_ICPART(1), ui32ICacheT1);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_ICPART(2), ui32ICacheT2);
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_SYSC_ICPART(3), ui32ICacheT3);
|
|
/* Enable instruction cache hits */
|
*pui32BootConf++ = META_CR_MMCU_ICACHE_CTRL;
|
*pui32BootConf++ = META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
META_CR_MMCU_ICACHE_CTRL,
|
META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
|
|
*pui32BootConf++ = 0x040000C0;
|
*pui32BootConf++ = 0;
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
0x040000C0, 0);
|
|
*ppui32BootConf = pui32BootConf;
|
}
|
|
/*!
|
*******************************************************************************
|
|
@Function ProcessLDRCommandStream
|
|
@Description Process the output of the Meta toolchain in the .LDR format
|
copying code and data sections into their final location and
|
passing some information to the Meta bootloader
|
|
@Input hPrivate : Implementation specific data
|
@Input pbLDR : Pointer to FW blob
|
@Input pvHostFWCodeAddr : Pointer to FW code
|
@Input pvHostFWDataAddr : Pointer to FW data
|
@Input pvHostFWCorememAddr : Pointer to FW coremem code
|
@Input ppui32BootConf : Pointer to bootloader data
|
|
@Return PVRSRV_ERROR
|
|
******************************************************************************/
|
static PVRSRV_ERROR ProcessLDRCommandStream(const void *hPrivate,
|
const IMG_BYTE* pbLDR,
|
void* pvHostFWCodeAddr,
|
void* pvHostFWDataAddr,
|
void* pvHostFWCorememAddr,
|
IMG_UINT32 **ppui32BootConf)
|
{
|
RGX_META_LDR_BLOCK_HDR *psHeader = (RGX_META_LDR_BLOCK_HDR *) pbLDR;
|
RGX_META_LDR_L1_DATA_BLK *psL1Data =
|
(RGX_META_LDR_L1_DATA_BLK*) ((IMG_UINT8 *) pbLDR + psHeader->ui32SLData);
|
|
IMG_UINT32 *pui32BootConf = *ppui32BootConf;
|
IMG_UINT32 ui32CorememSize = RGXGetFWCorememSize(hPrivate);
|
IMG_UINT32 ui32CorememCodeStartAddr = 0xFFFFFFFF;
|
|
RGXCommentLogInit(hPrivate, "**********************************************");
|
RGXCommentLogInit(hPrivate, "************** Begin LDR Parsing *************");
|
RGXCommentLogInit(hPrivate, "**********************************************");
|
|
while (psL1Data != NULL)
|
{
|
RGX_FW_SEGMENT_LIST sRGXFWSegList;
|
sRGXFWSegList.psRGXFWCodeSeg = asRGXMetaFWCodeSegments;
|
sRGXFWSegList.psRGXFWDataSeg = asRGXMetaFWDataSegments;
|
sRGXFWSegList.ui32CodeSegCount = RGXFW_META_NUM_CODE_SEGMENTS;
|
sRGXFWSegList.ui32DataSegCount = RGXFW_META_NUM_DATA_SEGMENTS;
|
|
if (RGX_META_LDR_BLK_IS_COMMENT(psL1Data->ui16Cmd))
|
{
|
/* Don't process comment blocks */
|
goto NextBlock;
|
}
|
|
switch (psL1Data->ui16Cmd & RGX_META_LDR_CMD_MASK)
|
{
|
case RGX_META_LDR_CMD_LOADMEM:
|
{
|
RGX_META_LDR_L2_DATA_BLK *psL2Block =
|
(RGX_META_LDR_L2_DATA_BLK*) (((IMG_UINT8 *) pbLDR) + psL1Data->aui32CmdData[1]);
|
IMG_UINT32 ui32Offset = psL1Data->aui32CmdData[0];
|
IMG_UINT32 ui32DataSize = psL2Block->ui16Length - 6 /* L2 Tag length and checksum */;
|
void *pvWriteAddr;
|
PVRSRV_ERROR eError;
|
|
if (RGX_META_IS_COREMEM_CODE(ui32Offset, ui32CorememSize))
|
{
|
if (ui32Offset < ui32CorememCodeStartAddr)
|
{
|
if (ui32CorememCodeStartAddr == 0xFFFFFFFF)
|
{
|
/* Take the first coremem code address as the coremem code start address */
|
ui32CorememCodeStartAddr = ui32Offset;
|
|
/* Also check that there is a valid allocation for the coremem code */
|
if (pvHostFWCorememAddr == NULL)
|
{
|
RGXErrorLogInit(hPrivate,
|
"ProcessLDRCommandStream: Coremem code found"
|
"but no coremem allocation available!");
|
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
else
|
{
|
/* The coremem addresses should be ordered in the LDR command stream */
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
|
/* Copy coremem data to buffer. The FW copies it to the actual coremem */
|
ui32Offset -= ui32CorememCodeStartAddr;
|
|
RGXMemCopy(hPrivate,
|
(void*)((IMG_UINT8 *)pvHostFWCorememAddr + ui32Offset),
|
psL2Block->aui32BlockData,
|
ui32DataSize);
|
}
|
else
|
{
|
/* Global range is aliased to local range */
|
ui32Offset &= ~META_MEM_GLOBAL_RANGE_BIT;
|
|
eError = FindMMUSegment(ui32Offset,
|
pvHostFWCodeAddr,
|
pvHostFWDataAddr,
|
&pvWriteAddr,
|
&sRGXFWSegList);
|
|
if (eError != PVRSRV_OK)
|
{
|
RGXErrorLogInit(hPrivate,
|
"ProcessLDRCommandStream: Addr 0x%x (size: %d) not found in any segment",
|
ui32Offset, ui32DataSize);
|
return eError;
|
}
|
|
/* Write to FW allocation only if available */
|
if (pvWriteAddr)
|
{
|
RGXMemCopy(hPrivate,
|
pvWriteAddr,
|
psL2Block->aui32BlockData,
|
ui32DataSize);
|
}
|
}
|
|
break;
|
}
|
case RGX_META_LDR_CMD_LOADCORE:
|
case RGX_META_LDR_CMD_LOADMMREG:
|
{
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
case RGX_META_LDR_CMD_START_THREADS:
|
{
|
/* Don't process this block */
|
break;
|
}
|
case RGX_META_LDR_CMD_ZEROMEM:
|
{
|
IMG_UINT32 ui32Offset = psL1Data->aui32CmdData[0];
|
IMG_UINT32 ui32ByteCount = psL1Data->aui32CmdData[1];
|
void *pvWriteAddr;
|
PVRSRV_ERROR eError;
|
|
if (RGX_META_IS_COREMEM_DATA(ui32Offset, ui32CorememSize))
|
{
|
/* cannot zero coremem directly */
|
break;
|
}
|
|
/* Global range is aliased to local range */
|
ui32Offset &= ~META_MEM_GLOBAL_RANGE_BIT;
|
|
eError = FindMMUSegment(ui32Offset,
|
pvHostFWCodeAddr,
|
pvHostFWDataAddr,
|
&pvWriteAddr,
|
&sRGXFWSegList);
|
|
if (eError != PVRSRV_OK)
|
{
|
RGXErrorLogInit(hPrivate,
|
"ProcessLDRCommandStream: Addr 0x%x (size: %d) not found in any segment",
|
ui32Offset, ui32ByteCount);
|
return eError;
|
}
|
|
/* Write to FW allocation only if available */
|
if (pvWriteAddr)
|
{
|
RGXMemSet(hPrivate, pvWriteAddr, 0, ui32ByteCount);
|
}
|
|
break;
|
}
|
case RGX_META_LDR_CMD_CONFIG:
|
{
|
RGX_META_LDR_L2_DATA_BLK *psL2Block =
|
(RGX_META_LDR_L2_DATA_BLK*) (((IMG_UINT8 *) pbLDR) + psL1Data->aui32CmdData[0]);
|
RGX_META_LDR_CFG_BLK *psConfigCommand = (RGX_META_LDR_CFG_BLK*) psL2Block->aui32BlockData;
|
IMG_UINT32 ui32L2BlockSize = psL2Block->ui16Length - 6 /* L2 Tag length and checksum */;
|
IMG_UINT32 ui32CurrBlockSize = 0;
|
|
while (ui32L2BlockSize)
|
{
|
switch (psConfigCommand->ui32Type)
|
{
|
case RGX_META_LDR_CFG_PAUSE:
|
case RGX_META_LDR_CFG_READ:
|
{
|
ui32CurrBlockSize = 8;
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
case RGX_META_LDR_CFG_WRITE:
|
{
|
IMG_UINT32 ui32RegisterOffset = psConfigCommand->aui32BlockData[0];
|
IMG_UINT32 ui32RegisterValue = psConfigCommand->aui32BlockData[1];
|
|
/* Only write to bootloader if we got a valid
|
* pointer to the FW code allocation
|
*/
|
if (pui32BootConf)
|
{
|
/* Do register write */
|
*pui32BootConf++ = ui32RegisterOffset;
|
*pui32BootConf++ = ui32RegisterValue;
|
}
|
|
RGXCommentLogInit(hPrivate, "Meta SP: [0x%08x] = 0x%08x",
|
ui32RegisterOffset, ui32RegisterValue);
|
|
ui32CurrBlockSize = 12;
|
break;
|
}
|
case RGX_META_LDR_CFG_MEMSET:
|
case RGX_META_LDR_CFG_MEMCHECK:
|
{
|
ui32CurrBlockSize = 20;
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
default:
|
{
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
ui32L2BlockSize -= ui32CurrBlockSize;
|
psConfigCommand = (RGX_META_LDR_CFG_BLK*) (((IMG_UINT8*) psConfigCommand) + ui32CurrBlockSize);
|
}
|
|
break;
|
}
|
default:
|
{
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
|
NextBlock:
|
|
if (psL1Data->ui32Next == 0xFFFFFFFF)
|
{
|
psL1Data = NULL;
|
}
|
else
|
{
|
psL1Data = (RGX_META_LDR_L1_DATA_BLK*) (((IMG_UINT8 *) pbLDR) + psL1Data->ui32Next);
|
}
|
}
|
|
*ppui32BootConf = pui32BootConf;
|
|
RGXCommentLogInit(hPrivate, "**********************************************");
|
RGXCommentLogInit(hPrivate, "************** End Loader Parsing ************");
|
RGXCommentLogInit(hPrivate, "**********************************************");
|
|
return PVRSRV_OK;
|
}
|
#endif /* RGX_FEATURE_META */
|
|
#if defined(RGX_FEATURE_MIPS) || defined(SUPPORT_KERNEL_SRVINIT)
|
/*!
|
*******************************************************************************
|
|
@Function ProcessELFCommandStream
|
|
@Description Process the output of the Mips toolchain in the .ELF format
|
copying code and data sections into their final location
|
|
@Input hPrivate : Implementation specific data
|
@Input pbELF : Pointer to FW blob
|
@Input pvHostFWCodeAddr : Pointer to FW code
|
@Input pvHostFWDataAddr : Pointer to FW data
|
|
@Return PVRSRV_ERROR
|
|
******************************************************************************/
|
static PVRSRV_ERROR ProcessELFCommandStream(const void *hPrivate,
|
const IMG_BYTE *pbELF,
|
void *pvHostFWCodeAddr,
|
void *pvHostFWDataAddr)
|
{
|
IMG_UINT32 ui32Entry;
|
RGX_MIPS_ELF_HDR *psHeader = (RGX_MIPS_ELF_HDR *)pbELF;
|
RGX_MIPS_ELF_PROGRAM_HDR *psProgramHeader =
|
(RGX_MIPS_ELF_PROGRAM_HDR *)(pbELF + psHeader->ui32Ephoff);
|
PVRSRV_ERROR eError;
|
|
for (ui32Entry = 0; ui32Entry < psHeader->ui32Ephnum; ui32Entry++, psProgramHeader++)
|
{
|
void *pvWriteAddr;
|
RGX_FW_SEGMENT_LIST sRGXFWSegList;
|
sRGXFWSegList.psRGXFWCodeSeg = asRGXMipsFWCodeSegments;
|
sRGXFWSegList.psRGXFWDataSeg = asRGXMipsFWDataSegments;
|
sRGXFWSegList.ui32CodeSegCount = RGXFW_MIPS_NUM_CODE_SEGMENTS;
|
sRGXFWSegList.ui32DataSegCount = RGXFW_MIPS_NUM_DATA_SEGMENTS;
|
|
/* Only consider loadable entries in the ELF segment table */
|
if (psProgramHeader->ui32Ptype != ELF_PT_LOAD) continue;
|
|
eError = FindMMUSegment(psProgramHeader->ui32Pvaddr,
|
pvHostFWCodeAddr,
|
pvHostFWDataAddr,
|
&pvWriteAddr,
|
&sRGXFWSegList);
|
|
if (eError != PVRSRV_OK)
|
{
|
RGXErrorLogInit(hPrivate,
|
"%s: Addr 0x%x (size: %d) not found in any segment",__func__,
|
psProgramHeader->ui32Pvaddr,
|
psProgramHeader->ui32Pfilesz);
|
return eError;
|
}
|
|
/* Write to FW allocation only if available */
|
if (pvWriteAddr)
|
{
|
RGXMemCopy(hPrivate,
|
pvWriteAddr,
|
(IMG_PBYTE)(pbELF + psProgramHeader->ui32Poffset),
|
psProgramHeader->ui32Pfilesz);
|
|
RGXMemSet(hPrivate,
|
(IMG_PBYTE)pvWriteAddr + psProgramHeader->ui32Pfilesz,
|
0,
|
psProgramHeader->ui32Pmemsz - psProgramHeader->ui32Pfilesz);
|
}
|
}
|
|
return PVRSRV_OK;
|
}
|
#endif /* RGX_FEATURE_MIPS */
|
|
|
PVRSRV_ERROR RGXGetFWImageAllocSize(const void *hPrivate,
|
IMG_DEVMEM_SIZE_T *puiFWCodeAllocSize,
|
IMG_DEVMEM_SIZE_T *puiFWDataAllocSize,
|
IMG_DEVMEM_SIZE_T *puiFWCorememAllocSize)
|
{
|
IMG_UINT32 i, ui32NumCodeSegments = 0, ui32NumDataSegments = 0;
|
RGX_FW_SEGMENT *pasRGXFWCodeSegments = NULL, *pasRGXFWDataSegments = NULL;
|
|
#if defined(SUPPORT_KERNEL_SRVINIT)
|
IMG_BOOL bMIPS = RGXDeviceHasFeatureInit(hPrivate, RGX_FEATURE_MIPS_BIT_MASK);
|
#elif defined(RGX_FEATURE_MIPS)
|
IMG_BOOL bMIPS = IMG_TRUE;
|
#else
|
IMG_BOOL bMIPS = IMG_FALSE;
|
#endif
|
|
#if defined(RGX_FEATURE_META) || defined(SUPPORT_KERNEL_SRVINIT)
|
if (!bMIPS)
|
{
|
pasRGXFWCodeSegments = asRGXMetaFWCodeSegments;
|
pasRGXFWDataSegments = asRGXMetaFWDataSegments;
|
ui32NumCodeSegments = RGXFW_META_NUM_CODE_SEGMENTS;
|
ui32NumDataSegments = RGXFW_META_NUM_DATA_SEGMENTS;
|
}
|
#endif
|
|
#if defined(RGX_FEATURE_MIPS) || defined(SUPPORT_KERNEL_SRVINIT)
|
if (bMIPS)
|
{
|
pasRGXFWCodeSegments = asRGXMipsFWCodeSegments;
|
pasRGXFWDataSegments = asRGXMipsFWDataSegments;
|
ui32NumCodeSegments = RGXFW_MIPS_NUM_CODE_SEGMENTS;
|
ui32NumDataSegments = RGXFW_MIPS_NUM_DATA_SEGMENTS;
|
}
|
#endif
|
|
*puiFWCodeAllocSize = 0;
|
*puiFWDataAllocSize = 0;
|
*puiFWCorememAllocSize = 0;
|
|
/* Calculate how much memory the FW needs for its code and data segments */
|
|
for(i = 0; i < ui32NumCodeSegments; i++) {
|
*puiFWCodeAllocSize += ((pasRGXFWCodeSegments + i)->ui32SegAllocSize);
|
}
|
|
for(i = 0; i < ui32NumDataSegments; i++) {
|
*puiFWDataAllocSize += ((pasRGXFWDataSegments + i)->ui32SegAllocSize);
|
}
|
|
*puiFWCorememAllocSize = RGXGetFWCorememSize(hPrivate);
|
|
if (*puiFWCorememAllocSize != 0)
|
{
|
*puiFWCorememAllocSize = *puiFWCorememAllocSize - RGX_META_COREMEM_DATA_SIZE;
|
}
|
|
if (bMIPS)
|
{
|
if ((*puiFWCodeAllocSize % RGXMIPSFW_PAGE_SIZE) != 0)
|
{
|
RGXErrorLogInit(hPrivate,
|
"%s: The MIPS FW code allocation is not"
|
" a multiple of the page size!", __func__);
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
|
if ((*puiFWDataAllocSize % RGXMIPSFW_PAGE_SIZE) != 0)
|
{
|
RGXErrorLogInit(hPrivate,
|
"%s: The MIPS FW data allocation is not"
|
" a multiple of the page size!", __func__);
|
return PVRSRV_ERROR_INIT_FAILURE;
|
}
|
}
|
|
return PVRSRV_OK;
|
}
|
|
|
PVRSRV_ERROR RGXProcessFWImage(const void *hPrivate,
|
const IMG_BYTE *pbRGXFirmware,
|
void *pvFWCode,
|
void *pvFWData,
|
void *pvFWCorememCode,
|
IMG_DEV_VIRTADDR *psFWCodeDevVAddrBase,
|
IMG_DEV_VIRTADDR *psFWDataDevVAddrBase,
|
IMG_DEV_VIRTADDR *psFWCorememDevVAddrBase,
|
RGXFWIF_DEV_VIRTADDR *psFWCorememFWAddr,
|
RGXFWIF_DEV_VIRTADDR *psRGXFwInit,
|
IMG_UINT32 ui32NumThreads,
|
IMG_UINT32 ui32MainThreadID)
|
{
|
PVRSRV_ERROR eError = PVRSRV_OK;
|
|
#if defined(SUPPORT_KERNEL_SRVINIT)
|
IMG_BOOL bMIPS = RGXDeviceHasFeatureInit(hPrivate, RGX_FEATURE_MIPS_BIT_MASK);
|
#elif defined(RGX_FEATURE_MIPS)
|
IMG_BOOL bMIPS = IMG_TRUE;
|
#else
|
IMG_BOOL bMIPS = IMG_FALSE;
|
#endif
|
|
#if defined(RGX_FEATURE_META) || defined(SUPPORT_KERNEL_SRVINIT)
|
if (!bMIPS)
|
{
|
IMG_UINT32 *pui32BootConf = NULL;
|
/* Skip bootloader configuration if a pointer to the FW code
|
* allocation is not available
|
*/
|
if (pvFWCode)
|
{
|
/* This variable points to the bootloader code which is mostly
|
* a sequence of <register address,register value> pairs
|
*/
|
pui32BootConf = ((IMG_UINT32*) pvFWCode) + RGXFW_BOOTLDR_CONF_OFFSET;
|
|
/* Slave port and JTAG accesses are privileged */
|
*pui32BootConf++ = META_CR_SYSC_JTAG_THREAD;
|
*pui32BootConf++ = META_CR_SYSC_JTAG_THREAD_PRIV_EN;
|
|
RGXFWConfigureSegMMU(hPrivate,
|
psFWCodeDevVAddrBase,
|
psFWDataDevVAddrBase,
|
&pui32BootConf);
|
}
|
|
/* Process FW image data stream */
|
eError = ProcessLDRCommandStream(hPrivate,
|
pbRGXFirmware,
|
pvFWCode,
|
pvFWData,
|
pvFWCorememCode,
|
&pui32BootConf);
|
if (eError != PVRSRV_OK)
|
{
|
RGXErrorLogInit(hPrivate, "RGXProcessFWImage: Processing FW image failed (%d)", eError);
|
return eError;
|
}
|
|
/* Skip bootloader configuration if a pointer to the FW code
|
* allocation is not available
|
*/
|
if (pvFWCode)
|
{
|
if ((ui32NumThreads == 0) || (ui32NumThreads > 2) || (ui32MainThreadID >= 2))
|
{
|
RGXErrorLogInit(hPrivate,
|
"ProcessFWImage: Wrong Meta threads configuration, using one thread only");
|
|
ui32NumThreads = 1;
|
ui32MainThreadID = 0;
|
}
|
|
RGXFWConfigureMetaCaches(hPrivate,
|
ui32NumThreads,
|
ui32MainThreadID,
|
&pui32BootConf);
|
|
/* Signal the end of the conf sequence */
|
*pui32BootConf++ = 0x0;
|
*pui32BootConf++ = 0x0;
|
|
/* The FW main argv arguments start here */
|
*pui32BootConf++ = psRGXFwInit->ui32Addr;
|
|
if ((RGXGetFWCorememSize(hPrivate) != 0) && (psFWCorememFWAddr != NULL))
|
{
|
*pui32BootConf++ = psFWCorememFWAddr->ui32Addr;
|
}
|
else
|
{
|
*pui32BootConf++ = 0;
|
}
|
|
#if defined(SUPPORT_KERNEL_SRVINIT)
|
if (RGXDeviceHasFeatureInit(hPrivate, RGX_FEATURE_META_DMA_BIT_MASK))
|
#elif defined(RGX_FEATURE_META_DMA)
|
if (IMG_TRUE)
|
#else
|
if (IMG_FALSE)
|
#endif
|
{
|
*pui32BootConf++ = (IMG_UINT32) (psFWCorememDevVAddrBase->uiAddr >> 32);
|
*pui32BootConf++ = (IMG_UINT32) psFWCorememDevVAddrBase->uiAddr;
|
}
|
else
|
{
|
*pui32BootConf++ = 0;
|
*pui32BootConf++ = 0;
|
}
|
|
}
|
}
|
#endif
|
|
#if defined(RGX_FEATURE_MIPS) || defined(SUPPORT_KERNEL_SRVINIT)
|
if (bMIPS)
|
{
|
/* Process FW image data stream */
|
eError = ProcessELFCommandStream(hPrivate,
|
pbRGXFirmware,
|
pvFWCode,
|
pvFWData);
|
if (eError != PVRSRV_OK)
|
{
|
RGXErrorLogInit(hPrivate, "RGXProcessFWImage: Processing FW image failed (%d)", eError);
|
return eError;
|
}
|
|
PVR_UNREFERENCED_PARAMETER(pvFWData); /* No need to touch the data segment in MIPS */
|
PVR_UNREFERENCED_PARAMETER(pvFWCorememCode); /* Coremem N/A in MIPS */
|
PVR_UNREFERENCED_PARAMETER(psFWCodeDevVAddrBase);
|
PVR_UNREFERENCED_PARAMETER(psFWDataDevVAddrBase);
|
PVR_UNREFERENCED_PARAMETER(psFWCorememDevVAddrBase);
|
PVR_UNREFERENCED_PARAMETER(psFWCorememFWAddr);
|
PVR_UNREFERENCED_PARAMETER(psRGXFwInit);
|
PVR_UNREFERENCED_PARAMETER(ui32NumThreads);
|
PVR_UNREFERENCED_PARAMETER(ui32MainThreadID);
|
}
|
#endif
|
|
return eError;
|
}
|
