/*************************************************************************/ /*!
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@File
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@Title RGX device node header file
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Header for the RGX device node
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(__RGXDEVICE_H__)
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#define __RGXDEVICE_H__
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#include "img_types.h"
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#include "pvrsrv_device_types.h"
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#include "mmu_common.h"
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#include "rgx_fwif_km.h"
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#include "rgx_fwif.h"
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#include "rgxscript.h"
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#include "cache_ops.h"
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#include "device.h"
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#include "osfunc.h"
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#include "rgxlayer_km_impl.h"
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#if defined(SUPPORT_WORKLOAD_ESTIMATION)
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#include "hash.h"
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#endif
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typedef struct _RGX_SERVER_COMMON_CONTEXT_ RGX_SERVER_COMMON_CONTEXT;
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typedef struct {
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DEVMEM_MEMDESC *psFWFrameworkMemDesc;
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IMG_DEV_VIRTADDR *psMCUFenceAddr;
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IMG_DEV_VIRTADDR *psResumeSignalAddr;
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} RGX_COMMON_CONTEXT_INFO;
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/*!
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******************************************************************************
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* Device state flags
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*****************************************************************************/
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#define RGXKM_DEVICE_STATE_ZERO_FREELIST (0x1 << 0) /*!< Zeroing the physical pages of reconstructed free lists */
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#define RGXKM_DEVICE_STATE_FTRACE_EN (0x1 << 1) /*!< Used to enable device FTrace thread to consume HWPerf data */
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#define RGXKM_DEVICE_STATE_DISABLE_DW_LOGGING_EN (0x1 << 2) /*!< Used to disable the Devices Watchdog logging */
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#define RGXKM_DEVICE_STATE_DUST_REQUEST_INJECT_EN (0x1 << 3) /*!< Used for validation to inject dust requests every TA/3D kick */
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/*!
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******************************************************************************
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* GPU DVFS Table
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*****************************************************************************/
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#define RGX_GPU_DVFS_TABLE_SIZE 100 /* DVFS Table size */
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#define RGX_GPU_DVFS_GET_INDEX(clockfreq) ((clockfreq) / 10000000) /* Assuming different GPU clocks are separated by at least 10MHz
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* WARNING: this macro must be used only with nominal values of
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* the GPU clock speed (the ones provided by the customer code) */
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#define RGX_GPU_DVFS_FIRST_CALIBRATION_TIME_US 25000 /* Time required to calibrate a clock frequency the first time */
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#define RGX_GPU_DVFS_TRANSITION_CALIBRATION_TIME_US 150000 /* Time required for a recalibration after a DVFS transition */
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#define RGX_GPU_DVFS_PERIODIC_CALIBRATION_TIME_US 10000000 /* Time before the next periodic calibration and correlation */
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typedef struct _RGX_GPU_DVFS_TABLE_
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{
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IMG_UINT64 ui64CalibrationCRTimestamp; /*!< CR timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
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IMG_UINT64 ui64CalibrationOSTimestamp; /*!< OS timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
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IMG_UINT64 ui64CalibrationCRTimediff; /*!< CR timediff used to calibrate GPU frequencies (calibration period) */
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IMG_UINT64 ui64CalibrationOSTimediff; /*!< OS timediff used to calibrate GPU frequencies (calibration period) */
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IMG_UINT32 ui32CalibrationPeriod; /*!< Threshold used to determine whether the current GPU frequency should be calibrated */
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IMG_UINT32 ui32CurrentDVFSId; /*!< Current table entry index */
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IMG_BOOL bAccumulatePeriod; /*!< Accumulate many consecutive periods to get a better calibration at the end */
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IMG_UINT32 aui32DVFSClock[RGX_GPU_DVFS_TABLE_SIZE]; /*!< DVFS clocks table (clocks in Hz) */
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} RGX_GPU_DVFS_TABLE;
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/*!
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******************************************************************************
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* GPU utilisation statistics
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*****************************************************************************/
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typedef struct _RGXFWIF_GPU_UTIL_STATS_
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{
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IMG_BOOL bValid; /* If TRUE, statistics are valid.
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FALSE if the driver couldn't get reliable stats. */
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IMG_UINT64 ui64GpuStatActiveHigh; /* GPU active high statistic */
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IMG_UINT64 ui64GpuStatActiveLow; /* GPU active low (i.e. TLA active only) statistic */
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IMG_UINT64 ui64GpuStatBlocked; /* GPU blocked statistic */
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IMG_UINT64 ui64GpuStatIdle; /* GPU idle statistic */
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IMG_UINT64 ui64GpuStatCumulative; /* Sum of active/blocked/idle stats */
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} RGXFWIF_GPU_UTIL_STATS;
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typedef struct _RGX_REG_CONFIG_
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{
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IMG_BOOL bEnabled;
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RGXFWIF_REG_CFG_TYPE eRegCfgTypeToPush;
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IMG_UINT32 ui32NumRegRecords;
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} RGX_REG_CONFIG;
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typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC;
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typedef struct
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{
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IMG_UINT32 ui32DustCount1;
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IMG_UINT32 ui32DustCount2;
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IMG_BOOL bToggle;
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} RGX_DUST_STATE;
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typedef struct _PVRSRV_DEVICE_FEATURE_CONFIG_
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{
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IMG_UINT64 ui64ErnsBrns;
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IMG_UINT64 ui64Features;
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IMG_UINT32 ui32B;
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IMG_UINT32 ui32V;
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IMG_UINT32 ui32N;
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IMG_UINT32 ui32C;
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IMG_UINT32 ui32NumClusters;
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IMG_UINT32 ui32CtrlStreamFormat;
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IMG_UINT32 ui32FBCDCArch;
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IMG_UINT32 ui32META;
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IMG_UINT32 ui32MCMB;
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IMG_UINT32 ui32MCMS;
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IMG_UINT32 ui32MDMACount;
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IMG_UINT32 ui32NIIP;
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IMG_UINT32 ui32PBW;
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IMG_UINT32 ui32STEArch;
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IMG_UINT32 ui32SVCE;
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IMG_UINT32 ui32SLCBanks;
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IMG_UINT32 ui32CacheLineSize;
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IMG_UINT32 ui32SLCSize;
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IMG_UINT32 ui32VASB;
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IMG_UINT32 ui32MAXDMCount;
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IMG_UINT32 ui32MAXDMMTSCount;
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IMG_UINT32 ui32MAXDustCount;
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#define MAX_BVNC_STRING_LEN (50)
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IMG_PCHAR pszBVNCString;
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}PVRSRV_DEVICE_FEATURE_CONFIG;
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/* there is a corresponding define in rgxapi.h */
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#define RGX_MAX_TIMER_QUERIES 16
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#if defined(SUPPORT_WORKLOAD_ESTIMATION)
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/* For the workload estimation return data array */
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/* The max amount of commands the MTS can have is 255, therefore 512 (LOG2 = 9)
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* is large enough to account for all corner cases.
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*/
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#define RETURN_DATA_ARRAY_SIZE_LOG2 (9)
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#define RETURN_DATA_ARRAY_SIZE ((1UL) << RETURN_DATA_ARRAY_SIZE_LOG2)
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#define RETURN_DATA_ARRAY_WRAP_MASK (RETURN_DATA_ARRAY_SIZE - 1)
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#define WORKLOAD_HASH_SIZE 64
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typedef struct _WORKEST_HOST_DATA_ WORKEST_HOST_DATA;
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typedef struct _RGX_WORKLOAD_TA3D_
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{
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IMG_UINT32 ui32RenderTargetSize;
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IMG_UINT32 ui32NumberOfDrawCalls;
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IMG_UINT32 ui32NumberOfIndices;
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IMG_UINT32 ui32NumberOfMRTs;
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} RGX_WORKLOAD_TA3D;
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typedef struct _WORKLOAD_MATCHING_DATA_
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{
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HASH_TABLE *psWorkloadDataHash;
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RGX_WORKLOAD_TA3D asWorkloadHashKeys[WORKLOAD_HASH_SIZE];
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IMG_UINT64 aui64HashCycleData[WORKLOAD_HASH_SIZE];
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IMG_UINT32 ui32HashArrayWO;
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POS_LOCK psWorkEstHashLock;
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} WORKLOAD_MATCHING_DATA;
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struct _WORKEST_HOST_DATA_{
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WORKLOAD_MATCHING_DATA sWorkloadMatchingDataTA;
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WORKLOAD_MATCHING_DATA sWorkloadMatchingData3D;
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IMG_UINT32 ui32WorkEstCCBReceived;
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};
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typedef struct _WORKEST_RETURN_DATA_ {
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WORKEST_HOST_DATA *psWorkEstHostData;
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WORKLOAD_MATCHING_DATA *psWorkloadMatchingData;
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RGX_WORKLOAD_TA3D sWorkloadCharacteristics;
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} WORKEST_RETURN_DATA;
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#endif
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typedef struct
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{
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#if defined(PDUMP)
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IMG_HANDLE hPdumpPages;
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#endif
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PG_HANDLE sPages;
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IMG_DEV_PHYADDR sPhysAddr;
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} RGX_MIPS_ADDRESS_TRAMPOLINE;
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/*!
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******************************************************************************
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* RGX Device info
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*****************************************************************************/
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typedef struct _PVRSRV_RGXDEV_INFO_
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{
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PVRSRV_DEVICE_NODE *psDeviceNode;
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PVRSRV_DEVICE_FEATURE_CONFIG sDevFeatureCfg;
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/* FIXME: This is a workaround due to having 2 inits but only 1 deinit */
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IMG_BOOL bDevInit2Done;
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IMG_BOOL bFirmwareInitialised;
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IMG_BOOL bPDPEnabled;
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IMG_HANDLE hDbgReqNotify;
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/* Kernel mode linear address of device registers */
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void *pvRegsBaseKM;
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/* FIXME: The alloc for this should go through OSAllocMem in future */
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IMG_HANDLE hRegMapping;
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/* System physical address of device registers*/
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IMG_CPU_PHYADDR sRegsPhysBase;
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/* Register region size in bytes */
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IMG_UINT32 ui32RegSize;
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PVRSRV_STUB_PBDESC *psStubPBDescListKM;
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/* Firmware memory context info */
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DEVMEM_CONTEXT *psKernelDevmemCtx;
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DEVMEM_HEAP *psFirmwareHeap;
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MMU_CONTEXT *psKernelMMUCtx;
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void *pvDeviceMemoryHeap;
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/* Kernel CCB */
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DEVMEM_MEMDESC *psKernelCCBCtlMemDesc; /*!< memdesc for Kernel CCB control */
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RGXFWIF_CCB_CTL *psKernelCCBCtl; /*!< kernel mapping for Kernel CCB control */
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DEVMEM_MEMDESC *psKernelCCBMemDesc; /*!< memdesc for Kernel CCB */
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IMG_UINT8 *psKernelCCB; /*!< kernel mapping for Kernel CCB */
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/* Firmware CCB */
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DEVMEM_MEMDESC *psFirmwareCCBCtlMemDesc; /*!< memdesc for Firmware CCB control */
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RGXFWIF_CCB_CTL *psFirmwareCCBCtl; /*!< kernel mapping for Firmware CCB control */
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DEVMEM_MEMDESC *psFirmwareCCBMemDesc; /*!< memdesc for Firmware CCB */
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IMG_UINT8 *psFirmwareCCB; /*!< kernel mapping for Firmware CCB */
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/* Workload Estimation Firmware CCB */
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DEVMEM_MEMDESC *psWorkEstFirmwareCCBCtlMemDesc; /*!< memdesc for Workload Estimation Firmware CCB control */
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RGXFWIF_CCB_CTL *psWorkEstFirmwareCCBCtl; /*!< kernel mapping for Workload Estimation Firmware CCB control */
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DEVMEM_MEMDESC *psWorkEstFirmwareCCBMemDesc; /*!< memdesc for Workload Estimation Firmware CCB */
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IMG_UINT8 *psWorkEstFirmwareCCB; /*!< kernel mapping for Workload Estimation Firmware CCB */
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IMG_BOOL bEnableFWPoisonOnFree; /*!< Enable poisoning of FW allocations when freed */
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IMG_BYTE ubFWPoisonOnFreeValue; /*!< Byte value used when poisoning FW allocations */
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/*
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if we don't preallocate the pagetables we must
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insert newly allocated page tables dynamically
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*/
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void *pvMMUContextList;
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IMG_UINT32 ui32ClkGateStatusReg;
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IMG_UINT32 ui32ClkGateStatusMask;
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RGX_SCRIPTS *psScripts;
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DEVMEM_MEMDESC *psRGXFWCodeMemDesc;
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IMG_DEV_VIRTADDR sFWCodeDevVAddrBase;
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DEVMEM_MEMDESC *psRGXFWDataMemDesc;
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IMG_DEV_VIRTADDR sFWDataDevVAddrBase;
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RGX_MIPS_ADDRESS_TRAMPOLINE sTrampoline;
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DEVMEM_MEMDESC *psRGXFWCorememMemDesc;
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IMG_DEV_VIRTADDR sFWCorememCodeDevVAddrBase;
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RGXFWIF_DEV_VIRTADDR sFWCorememCodeFWAddr;
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#if defined(RGXFW_ALIGNCHECKS)
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DEVMEM_MEMDESC *psRGXFWAlignChecksMemDesc;
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#endif
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DEVMEM_MEMDESC *psRGXFWSigTAChecksMemDesc;
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IMG_UINT32 ui32SigTAChecksSize;
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DEVMEM_MEMDESC *psRGXFWSig3DChecksMemDesc;
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IMG_UINT32 ui32Sig3DChecksSize;
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DEVMEM_MEMDESC *psRGXFWSigRTChecksMemDesc;
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IMG_UINT32 ui32SigRTChecksSize;
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DEVMEM_MEMDESC *psRGXFWSigSHChecksMemDesc;
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IMG_UINT32 ui32SigSHChecksSize;
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#if defined (PDUMP)
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IMG_BOOL bDumpedKCCBCtlAlready;
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#endif
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#if defined(PVRSRV_GPUVIRT_GUESTDRV)
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/*
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Guest drivers do not support these functionalities:
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- H/W perf & device power management
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- F/W initialization & management
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- GPU dvfs, trace & utilization
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*/
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DEVMEM_MEMDESC *psRGXFWIfInitMemDesc;
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RGXFWIF_DEV_VIRTADDR sFWInitFWAddr;
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#else
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DEVMEM_MEMDESC *psRGXFWIfTraceBufCtlMemDesc; /*!< memdesc of trace buffer control structure */
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DEVMEM_MEMDESC *psRGXFWIfTraceBufferMemDesc[RGXFW_THREAD_NUM]; /*!< memdesc of actual FW trace (log) buffer(s) */
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RGXFWIF_TRACEBUF *psRGXFWIfTraceBuf; /* structure containing trace control data and actual trace buffer */
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DEVMEM_MEMDESC *psRGXFWIfHWRInfoBufCtlMemDesc;
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RGXFWIF_HWRINFOBUF *psRGXFWIfHWRInfoBuf;
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DEVMEM_MEMDESC *psRGXFWIfGpuUtilFWCbCtlMemDesc;
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RGXFWIF_GPU_UTIL_FWCB *psRGXFWIfGpuUtilFWCb;
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DEVMEM_MEMDESC *psRGXFWIfHWPerfBufMemDesc;
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IMG_BYTE *psRGXFWIfHWPerfBuf;
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IMG_UINT32 ui32RGXFWIfHWPerfBufSize; /* in bytes */
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DEVMEM_MEMDESC *psRGXFWIfCorememDataStoreMemDesc;
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DEVMEM_MEMDESC *psRGXFWIfRegCfgMemDesc;
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DEVMEM_MEMDESC *psRGXFWIfHWPerfCountersMemDesc;
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DEVMEM_MEMDESC *psRGXFWIfInitMemDesc;
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RGXFWIF_DEV_VIRTADDR sFWInitFWAddr;
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DEVMEM_MEMDESC *psRGXFWIfRuntimeCfgMemDesc;
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RGXFWIF_RUNTIME_CFG *psRGXFWIfRuntimeCfg;
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#if defined(SUPPORT_PVRSRV_GPUVIRT)
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/* Additional guest firmware memory context info */
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DEVMEM_HEAP *psGuestFirmwareHeap[RGXFW_NUM_OS-1];
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DEVMEM_MEMDESC *psGuestFirmwareMemDesc[RGXFW_NUM_OS-1];
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#endif
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DEVMEM_MEMDESC *psMETAT1StackMemDesc;
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#if defined(SUPPORT_WORKLOAD_ESTIMATION)
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/* Array to store data needed for workload estimation when a workload
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* has finished and its cycle time is returned to the host.
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*/
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WORKEST_RETURN_DATA asReturnData[RETURN_DATA_ARRAY_SIZE];
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IMG_UINT32 ui32ReturnDataWO;
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#endif
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#if defined (SUPPORT_PDVFS)
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/**
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* Host memdesc and pointer to memory containing core clock rate in Hz.
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* Firmware (PDVFS) updates the memory on changing the core clock rate over
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* GPIO.
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* Note: Shared memory needs atomic access from Host driver and firmware,
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* hence size should not be greater than memory transaction granularity.
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* Currently it's is chosen to be 32 bits.
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*/
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DEVMEM_MEMDESC *psRGXFWIFCoreClkRateMemDesc;
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volatile IMG_UINT32 *pui32RGXFWIFCoreClkRate;
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/**
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* Last sampled core clk rate.
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*/
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volatile IMG_UINT32 ui32CoreClkRateSnapshot;
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#endif
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/*
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HWPerf data for the RGX device
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*/
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POS_LOCK hHWPerfLock; /*! Critical section lock that protects HWPerf code
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* from multiple thread duplicate init/deinit
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* and loss/freeing of FW & Host resources while in
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* use in another thread e.g. MSIR. */
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IMG_UINT64 ui64HWPerfFilter; /*! Event filter for FW events (settable by AppHint) */
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IMG_HANDLE hHWPerfStream; /*! TL Stream buffer (L2) for firmware event stream */
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IMG_UINT32 ui32HWPerfHostFilter; /*! Event filter for HWPerfHost stream (settable by AppHint) */
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POS_LOCK hLockHWPerfHostStream; /*! Lock guarding access to HWPerfHost stream from multiple threads */
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IMG_HANDLE hHWPerfHostStream; /*! TL Stream buffer for host only event stream */
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IMG_UINT32 ui32HWPerfHostBufSize; /*! Host side buffer size in bytes */
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IMG_UINT32 ui32HWPerfHostNextOrdinal; /*! Ordinal number for HWPerfHost events */
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#if defined(SUPPORT_GPUTRACE_EVENTS)
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void *pvGpuFtraceData;
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#endif
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/* Poll data for detecting firmware fatal errors */
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IMG_UINT32 aui32CrLastPollAddr[RGXFW_THREAD_NUM];
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IMG_UINT32 ui32KCCBCmdsExecutedLastTime;
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IMG_BOOL bKCCBCmdsWaitingLastTime;
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IMG_UINT32 ui32GEOTimeoutsLastTime;
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/* Client stall detection */
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IMG_UINT32 ui32StalledClientMask;
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#endif
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IMG_BOOL bWorkEstEnabled;
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IMG_BOOL bPDVFSEnabled;
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void *pvLISRData;
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void *pvMISRData;
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void *pvAPMISRData;
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RGX_ACTIVEPM_CONF eActivePMConf;
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volatile IMG_UINT32 aui32SampleIRQCount[RGXFW_THREAD_NUM];
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DEVMEM_MEMDESC *psRGXFaultAddressMemDesc;
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DEVMEM_MEMDESC *psRGXFWHWBRN37200MemDesc;
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DEVMEM_MEMDESC *psSLC3FenceMemDesc;
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/* If we do 10 deferred memory allocations per second, then the ID would wrap around after 13 years */
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IMG_UINT32 ui32ZSBufferCurrID; /*!< ID assigned to the next deferred devmem allocation */
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IMG_UINT32 ui32FreelistCurrID; /*!< ID assigned to the next freelist */
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IMG_UINT32 ui32RPMFreelistCurrID; /*!< ID assigned to the next RPM freelist */
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POS_LOCK hLockZSBuffer; /*!< Lock to protect simultaneous access to ZSBuffers */
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DLLIST_NODE sZSBufferHead; /*!< List of on-demand ZSBuffers */
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POS_LOCK hLockFreeList; /*!< Lock to protect simultaneous access to Freelists */
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DLLIST_NODE sFreeListHead; /*!< List of growable Freelists */
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POS_LOCK hLockRPMFreeList; /*!< Lock to protect simultaneous access to RPM Freelists */
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DLLIST_NODE sRPMFreeListHead; /*!< List of growable RPM Freelists */
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POS_LOCK hLockRPMContext; /*!< Lock to protect simultaneous access to RPM contexts */
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PSYNC_PRIM_CONTEXT hSyncPrimContext;
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PVRSRV_CLIENT_SYNC_PRIM *psPowSyncPrim;
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IMG_UINT32 ui32ActivePMReqOk;
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IMG_UINT32 ui32ActivePMReqDenied;
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IMG_UINT32 ui32ActivePMReqTotal;
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IMG_HANDLE hProcessQueuesMISR;
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IMG_UINT32 ui32DeviceFlags; /*!< Flags to track general device state */
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/* Timer Queries */
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IMG_UINT32 ui32ActiveQueryId; /*!< id of the active line */
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IMG_BOOL bSaveStart; /*!< save the start time of the next kick on the device*/
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IMG_BOOL bSaveEnd; /*!< save the end time of the next kick on the device*/
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DEVMEM_MEMDESC *psStartTimeMemDesc; /*!< memdesc for Start Times */
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IMG_UINT64 *pui64StartTimeById; /*!< CPU mapping of the above */
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DEVMEM_MEMDESC *psEndTimeMemDesc; /*!< memdesc for End Timer */
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IMG_UINT64 *pui64EndTimeById; /*!< CPU mapping of the above */
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IMG_UINT32 aui32ScheduledOnId[RGX_MAX_TIMER_QUERIES]; /*!< kicks Scheduled on QueryId */
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DEVMEM_MEMDESC *psCompletedMemDesc; /*!< kicks Completed on QueryId */
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IMG_UINT32 *pui32CompletedById; /*!< CPU mapping of the above */
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#if !defined(PVRSRV_GPUVIRT_GUESTDRV)
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/* GPU DVFS Table */
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RGX_GPU_DVFS_TABLE *psGpuDVFSTable;
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/* Pointer to function returning the GPU utilisation statistics since the last
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* time the function was called. Supports different users at the same time.
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*
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* psReturnStats [out]: GPU utilisation statistics (active high/active low/idle/blocked)
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* in microseconds since the last time the function was called
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* by a specific user (identified by hGpuUtilUser)
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*
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* Returns PVRSRV_OK in case the call completed without errors,
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* some other value otherwise.
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*/
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PVRSRV_ERROR (*pfnGetGpuUtilStats) (PVRSRV_DEVICE_NODE *psDeviceNode,
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IMG_HANDLE hGpuUtilUser,
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RGXFWIF_GPU_UTIL_STATS *psReturnStats);
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#endif
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POS_LOCK hGPUUtilLock;
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/* Register configuration */
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RGX_REG_CONFIG sRegCongfig;
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IMG_BOOL bRGXPowered;
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DLLIST_NODE sMemoryContextList;
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POSWR_LOCK hRenderCtxListLock;
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POSWR_LOCK hComputeCtxListLock;
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POSWR_LOCK hTransferCtxListLock;
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POSWR_LOCK hTDMCtxListLock;
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POSWR_LOCK hRaytraceCtxListLock;
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POSWR_LOCK hMemoryCtxListLock;
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POSWR_LOCK hKickSyncCtxListLock;
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/* Linked list of deferred KCCB commands due to a full KCCB */
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DLLIST_NODE sKCCBDeferredCommandsListHead;
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/* Linked lists of contexts on this device */
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DLLIST_NODE sRenderCtxtListHead;
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DLLIST_NODE sComputeCtxtListHead;
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DLLIST_NODE sTransferCtxtListHead;
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DLLIST_NODE sTDMCtxtListHead;
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DLLIST_NODE sRaytraceCtxtListHead;
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DLLIST_NODE sKickSyncCtxtListHead;
|
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DLLIST_NODE sCommonCtxtListHead;
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IMG_UINT32 ui32CommonCtxtCurrentID; /*!< ID assigned to the next common context */
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#if defined(SUPPORT_PAGE_FAULT_DEBUG)
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POS_LOCK hDebugFaultInfoLock; /*!< Lock to protect the debug fault info list */
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POS_LOCK hMMUCtxUnregLock; /*!< Lock to protect list of unregistered MMU contexts */
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#endif
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POS_LOCK hNMILock; /*!< Lock to protect NMI operations */
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RGX_DUST_STATE sDustReqState;
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RGX_POWER_LAYER_PARAMS sPowerParams;
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RGXFWIF_DM eBPDM; /*!< Current breakpoint data master */
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IMG_BOOL bBPSet; /*!< A Breakpoint has been set */
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IMG_UINT32 ui32CoherencyTestsDone;
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} PVRSRV_RGXDEV_INFO;
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|
|
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typedef struct _RGX_TIMING_INFORMATION_
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{
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/*! GPU default voltage */
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IMG_UINT32 ui32CoreVoltage;
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/*! GPU default core clock speed in Hz */
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IMG_UINT32 ui32CoreClockSpeed;
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/*! Active Power Management: GPU actively requests the host driver to be powered off */
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IMG_BOOL bEnableActivePM;
|
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/*! Enable the GPU to power off internal Power Islands independently from the host driver */
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IMG_BOOL bEnableRDPowIsland;
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/*! Active Power Management: Delay between the GPU idle and the request to the host */
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IMG_UINT32 ui32ActivePMLatencyms;
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} RGX_TIMING_INFORMATION;
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typedef struct _RGX_DATA_
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{
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/*! Timing information */
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RGX_TIMING_INFORMATION *psRGXTimingInfo;
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IMG_BOOL bHasTDFWCodePhysHeap;
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IMG_UINT32 uiTDFWCodePhysHeapID;
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IMG_BOOL bHasTDSecureBufPhysHeap;
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IMG_UINT32 uiTDSecureBufPhysHeapID;
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} RGX_DATA;
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|
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/*
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RGX PDUMP register bank name (prefix)
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*/
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#define RGX_PDUMPREG_NAME "RGXREG"
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#endif /* __RGXDEVICE_H__ */
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