/*************************************************************************/ /*!
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@File rgx_mips.h
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@Title
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Platform RGX
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@Description RGX MIPS definitions, user space
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined (__RGX_MIPS_H__)
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#define __RGX_MIPS_H__
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/*
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* Utility defines for memory management
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*/
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#define RGXMIPSFW_LOG2_PAGE_SIZE (12)
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#define RGXMIPSFW_LOG2_PAGE_SIZE_64K (16)
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/* Page size */
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#define RGXMIPSFW_PAGE_SIZE (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_PAGE_MASK (RGXMIPSFW_PAGE_SIZE - 1)
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#define RGXMIPSFW_LOG2_PAGETABLE_PAGE_SIZE (15)
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#define RGXMIPSFW_LOG2_PTE_ENTRY_SIZE (2)
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/* Page mask MIPS register setting for bigger pages */
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#define RGXMIPSFW_PAGE_MASK_16K (0x00007800)
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#define RGXMIPSFW_PAGE_MASK_64K (0x0001F800)
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/* Page Frame Number of the entry lo */
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#define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
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#define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6)
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/* Dirty Valid And Global bits in entry lo */
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#define RGXMIPSFW_ENTRYLO_DVG_MASK (0x00000007)
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/* Dirty Valid And Global bits + caching policy in entry lo */
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#define RGXMIPSFW_ENTRYLO_DVGC_MASK (0x0000003F)
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/* Total number of TLB entries */
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#define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16)
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/*
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* Firmware physical layout
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*/
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#define RGXMIPSFW_CODE_BASE_PAGE (0x0)
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#define RGXMIPSFW_CODE_OFFSET (RGXMIPSFW_CODE_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#if defined(SUPPORT_TRUSTED_DEVICE)
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/* Clean way of getting a 256K allocation (62 + 1 + 1 pages) without using too many ifdefs */
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/* This will need to be changed if the non-secure builds reach this amount of pages */
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#define RGXMIPSFW_CODE_NUMPAGES (62)
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#else
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#define RGXMIPSFW_CODE_NUMPAGES (38)
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#endif
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#define RGXMIPSFW_CODE_SIZE (RGXMIPSFW_CODE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_EXCEPTIONSVECTORS_BASE_PAGE (RGXMIPSFW_CODE_BASE_PAGE + RGXMIPSFW_CODE_NUMPAGES)
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#define RGXMIPSFW_EXCEPTIONSVECTORS_OFFSET (RGXMIPSFW_EXCEPTIONSVECTORS_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_EXCEPTIONSVECTORS_NUMPAGES (1)
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#define RGXMIPSFW_EXCEPTIONSVECTORS_SIZE (RGXMIPSFW_EXCEPTIONSVECTORS_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_BOOT_NMI_CODE_BASE_PAGE (RGXMIPSFW_EXCEPTIONSVECTORS_BASE_PAGE + RGXMIPSFW_EXCEPTIONSVECTORS_NUMPAGES)
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#define RGXMIPSFW_BOOT_NMI_CODE_OFFSET (RGXMIPSFW_BOOT_NMI_CODE_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_BOOT_NMI_CODE_NUMPAGES (1)
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#define RGXMIPSFW_BOOT_NMI_CODE_SIZE (RGXMIPSFW_BOOT_NMI_CODE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_DATA_BASE_PAGE (0x0)
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#define RGXMIPSFW_DATA_OFFSET (RGXMIPSFW_DATA_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_DATA_NUMPAGES (22)
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#define RGXMIPSFW_DATA_SIZE (RGXMIPSFW_DATA_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_BOOT_NMI_DATA_BASE_PAGE (RGXMIPSFW_DATA_BASE_PAGE + RGXMIPSFW_DATA_NUMPAGES)
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#define RGXMIPSFW_BOOT_NMI_DATA_OFFSET (RGXMIPSFW_BOOT_NMI_DATA_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_BOOT_NMI_DATA_NUMPAGES (1)
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#define RGXMIPSFW_BOOT_NMI_DATA_SIZE (RGXMIPSFW_BOOT_NMI_DATA_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_STACK_BASE_PAGE (RGXMIPSFW_BOOT_NMI_DATA_BASE_PAGE + RGXMIPSFW_BOOT_NMI_DATA_NUMPAGES)
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#define RGXMIPSFW_STACK_OFFSET (RGXMIPSFW_STACK_BASE_PAGE << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_STACK_NUMPAGES (1)
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#define RGXMIPSFW_STACK_SIZE (RGXMIPSFW_STACK_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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/*
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* Pages to trampoline problematic physical addresses:
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* - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN : 0x1FC0_0000
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* - RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN : 0x1FC0_1000
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* - RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN : 0x1FC0_2000
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* - (benign trampoline) : 0x1FC0_3000
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* that would otherwise be erroneously remapped by the MIPS wrapper
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* (see "Firmware virtual layout and remap configuration" section below)
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*/
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#define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2)
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#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
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#define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE)
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#define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1<<RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a))
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/*
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* Firmware virtual layout and remap configuration
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*/
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/*
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* For each remap region we define:
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* - the virtual base used by the Firmware to access code/data through that region
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* - the microAptivAP physical address correspondent to the virtual base address,
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* used as input address and remapped to the actual physical address
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* - log2 of size of the region remapped by the MIPS wrapper, i.e. number of bits from
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* the bottom of the base input address that survive onto the output address
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* (this defines both the alignment and the maximum size of the remapped region)
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* - one or more code/data segments within the remapped region
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*/
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/* Boot remap setup */
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#define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000)
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#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000)
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#define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE)
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/* Data remap setup */
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#define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000)
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#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000)
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#define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE)
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/* Code remap setup */
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#define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000)
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#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000)
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#define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE)
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/* Fixed TLB setup */
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#define RGXMIPSFW_PT_VIRTUAL_BASE (0xCF000000)
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#define RGXMIPSFW_REGISTERS_VIRTUAL_BASE (0xCF400000)
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#define RGXMIPSFW_STACK_VIRTUAL_BASE (0xCF600000)
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#if defined(SUPPORT_TRUSTED_DEVICE)
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/* The extra fixed TLB entries are used in security builds for the FW code */
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#define RGXMIPSFW_NUMBER_OF_RESERVED_TLB (5)
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#else
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#define RGXMIPSFW_NUMBER_OF_RESERVED_TLB (3)
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#endif
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/* Firmware heap setup */
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#define RGXMIPSFW_FIRMWARE_HEAP_BASE (0xC0000000)
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#define RGXMIPSFW_CODE_VIRTUAL_BASE (RGXMIPSFW_FIRMWARE_HEAP_BASE)
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/* The data virtual base takes into account the exception vectors page
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* and the boot code page mapped in the FW heap together with the FW code
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* (we can only map Firmware code allocation as a whole) */
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#define RGXMIPSFW_DATA_VIRTUAL_BASE (RGXMIPSFW_CODE_VIRTUAL_BASE + RGXMIPSFW_CODE_SIZE + \
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RGXMIPSFW_EXCEPTIONSVECTORS_SIZE + RGXMIPSFW_BOOT_NMI_CODE_SIZE)
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/*
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* Bootloader configuration data
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*/
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/* Bootloader configuration offset within the bootloader/NMI data page */
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#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0)
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/* Offsets of bootloader configuration parameters in 64-bit words */
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#define RGXMIPSFW_ROGUE_REGS_BASE_PHYADDR_OFFSET (0x0)
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#define RGXMIPSFW_PAGE_TABLE_BASE_PHYADDR_OFFSET (0x1)
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#define RGXMIPSFW_STACKPOINTER_PHYADDR_OFFSET (0x2)
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#define RGXMIPSFW_RESERVED_FUTURE_OFFSET (0x3)
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#define RGXMIPSFW_FWINIT_VIRTADDR_OFFSET (0x4)
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/*
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* MIPS Fence offset in the bootloader/NMI data page
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*/
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#define RGXMIPSFW_FENCE_OFFSET (0x80)
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/*
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* NMI shared data
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*/
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/* Base address of the shared data within the bootloader/NMI data page */
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#define RGXMIPSFW_NMI_SHARED_DATA_BASE (0x100)
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/* Size used by Debug dump data */
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#define RGXMIPSFW_NMI_SHARED_SIZE (0x128)
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/* Offsets in the NMI shared area in 32-bit words */
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#define RGXMIPSFW_NMI_SYNC_FLAG_OFFSET (0x0)
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#define RGXMIPSFW_NMI_STATE_OFFSET (0x1)
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/*
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* MIPS fault data
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*/
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/* Base address of the fault data within the bootloader/NMI data page */
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#define RGXMIPSFW_FAULT_DATA_BASE (0x280)
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/* The things that follow are excluded when compiling assembly sources*/
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#if !defined (RGXMIPSFW_ASSEMBLY_CODE)
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#include "img_types.h"
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#include "km/rgxdefs_km.h"
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#define RGXMIPSFW_GET_OFFSET_IN_DWORDS(offset) (offset / sizeof(IMG_UINT32))
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#define RGXMIPSFW_GET_OFFSET_IN_QWORDS(offset) (offset / sizeof(IMG_UINT64))
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/* Used for compatibility checks */
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#define RGXMIPSFW_ARCHTYPE_VER_CLRMSK (0xFFFFE3FFU)
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#define RGXMIPSFW_ARCHTYPE_VER_SHIFT (10U)
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#define RGXMIPSFW_CORE_ID_VALUE (0x001U)
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#define RGXFW_PROCESSOR_MIPS "MIPS"
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/* microAptivAP cache line size */
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#define RGXMIPSFW_MICROAPTIVEAP_CACHELINE_SIZE (16U)
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/* The SOCIF transactions are identified with the top 16 bits of the physical address emitted by the MIPS */
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#define RGXMIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN (16U)
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/* Values to put in the MIPS selectors for performance counters*/
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#define RGXMIPSFW_PERF_COUNT_CTRL_ICACHE_ACCESSES_C0 (9U) /* Icache accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_ICACHE_MISSES_C1 (9U) /* Icache misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_DCACHE_ACCESSES_C0 (10U) /* Dcache accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_DCACHE_MISSES_C1 (11U) /* Dcache misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_ITLB_INSTR_ACCESSES_C0 (5U) /* ITLB instruction accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_JTLB_INSTR_MISSES_C1 (7U) /* JTLB instruction accesses misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_INSTR_COMPLETED_C0 (1U) /* Instructions completed in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_JTLB_DATA_MISSES_C1 (8U) /* JTLB data misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_EVENT_SHIFT (5U) /* Shift for the Event field in the MIPS perf ctrl registers */
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/* Additional flags for performance counters. See MIPS manual for further reference*/
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_USER_MODE (8U)
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_KERNEL_MODE (2U)
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_EXL (1U)
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#define RGXMIPSFW_C0_NBHWIRQ 8
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/* Macros to decode C0_Cause register */
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#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2)
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/* Use only when Coprocessor Unusable exception */
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#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3)
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#define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10)
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#define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1 << 21)
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#define RGXMIPSFW_C0_CAUSE_IV (1 << 23)
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#define RGXMIPSFW_C0_CAUSE_IC (1 << 25)
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#define RGXMIPSFW_C0_CAUSE_PCIPENDING (1 << 26)
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#define RGXMIPSFW_C0_CAUSE_TIPENDING (1 << 30)
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/* Macros to decode C0_Debug register */
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#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f)
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#define RGXMIPSFW_C0_DEBUG_DSS (1 << 0)
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#define RGXMIPSFW_C0_DEBUG_DBP (1 << 1)
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#define RGXMIPSFW_C0_DEBUG_DDBL (1 << 2)
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#define RGXMIPSFW_C0_DEBUG_DDBS (1 << 3)
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#define RGXMIPSFW_C0_DEBUG_DIB (1 << 4)
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#define RGXMIPSFW_C0_DEBUG_DINT (1 << 5)
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#define RGXMIPSFW_C0_DEBUG_DIBIMPR (1 << 6)
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#define RGXMIPSFW_C0_DEBUG_DDBLIMPR (1 << 18)
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#define RGXMIPSFW_C0_DEBUG_DDBSIMPR (1 << 19)
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#define RGXMIPSFW_C0_DEBUG_IEXI (1 << 20)
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#define RGXMIPSFW_C0_DEBUG_DBUSEP (1 << 21)
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#define RGXMIPSFW_C0_DEBUG_CACHEEP (1 << 22)
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#define RGXMIPSFW_C0_DEBUG_MCHECKP (1 << 23)
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#define RGXMIPSFW_C0_DEBUG_IBUSEP (1 << 24)
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#define RGXMIPSFW_C0_DEBUG_DM (1 << 30)
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#define RGXMIPSFW_C0_DEBUG_DBD (1 << 31)
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/* ELF format defines */
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#define ELF_PT_LOAD (0x1U) /* Program header identifier as Load */
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#define ELF_SHT_SYMTAB (0x2U) /* Section identifier as Symbol Table */
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#define ELF_SHT_STRTAB (0x3U) /* Section identifier as String Table */
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#define MAX_STRTAB_NUM (0x8U) /* Maximum number of string table in the firmware ELF file */
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/* Redefined structs of ELF format */
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typedef struct
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{
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IMG_UINT8 ui32Eident[16];
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IMG_UINT16 ui32Etype;
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IMG_UINT16 ui32Emachine;
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IMG_UINT32 ui32Eversion;
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IMG_UINT32 ui32Eentry;
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IMG_UINT32 ui32Ephoff;
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IMG_UINT32 ui32Eshoff;
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IMG_UINT32 ui32Eflags;
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IMG_UINT16 ui32Eehsize;
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IMG_UINT16 ui32Ephentsize;
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IMG_UINT16 ui32Ephnum;
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IMG_UINT16 ui32Eshentsize;
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IMG_UINT16 ui32Eshnum;
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IMG_UINT16 ui32Eshtrndx;
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} RGX_MIPS_ELF_HDR;
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typedef struct
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{
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IMG_UINT32 ui32Stname;
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IMG_UINT32 ui32Stvalue;
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IMG_UINT32 ui32Stsize;
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IMG_UINT8 ui32Stinfo;
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IMG_UINT8 ui32Stother;
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IMG_UINT16 ui32Stshndx;
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} RGX_MIPS_ELF_SYM;
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typedef struct
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{
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IMG_UINT32 ui32Shname;
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IMG_UINT32 ui32Shtype;
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IMG_UINT32 ui32Shflags;
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IMG_UINT32 ui32Shaddr;
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IMG_UINT32 ui32Shoffset;
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IMG_UINT32 ui32Shsize;
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IMG_UINT32 ui32Shlink;
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IMG_UINT32 ui32Shinfo;
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IMG_UINT32 ui32Shaddralign;
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IMG_UINT32 ui32Shentsize;
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} RGX_MIPS_ELF_SHDR;
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typedef struct
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{
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IMG_UINT32 ui32Ptype;
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IMG_UINT32 ui32Poffset;
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IMG_UINT32 ui32Pvaddr;
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IMG_UINT32 ui32Ppaddr;
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IMG_UINT32 ui32Pfilesz;
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IMG_UINT32 ui32Pmemsz;
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IMG_UINT32 ui32Pflags;
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IMG_UINT32 ui32Palign;
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} RGX_MIPS_ELF_PROGRAM_HDR;
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#define RGXMIPSFW_TLB_GET_MASK(ENTRY_PAGE_MASK) (((ENTRY_PAGE_MASK) >> 13) & 0xffffU)
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#define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13)
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#define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U)
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#define RGXMIPSFW_TLB_GET_PFN(ENTRY_LO) (((ENTRY_LO) >> 6) & 0xfffffU)
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#define RGXMIPSFW_TLB_GET_INHIBIT(ENTRY_LO) (((ENTRY_LO) >> 30) & 0x3U)
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#define RGXMIPSFW_TLB_GET_DGV(ENTRY_LO) ((ENTRY_LO) & 0x7U)
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#define RGXMIPSFW_TLB_GLOBAL (1U)
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#define RGXMIPSFW_TLB_VALID (1U << 1)
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#define RGXMIPSFW_TLB_DIRTY (1U << 2)
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#define RGXMIPSFW_TLB_XI (1U << 30)
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#define RGXMIPSFW_TLB_RI (1U << 31)
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typedef struct {
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IMG_UINT32 ui32TLBPageMask;
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IMG_UINT32 ui32TLBHi;
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IMG_UINT32 ui32TLBLo0;
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IMG_UINT32 ui32TLBLo1;
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} RGX_MIPS_TLB_ENTRY;
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typedef struct {
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IMG_UINT32 ui32ErrorEPC;
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IMG_UINT32 ui32StatusRegister;
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IMG_UINT32 ui32CauseRegister;
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IMG_UINT32 ui32BadRegister;
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IMG_UINT32 ui32EPC;
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IMG_UINT32 ui32SP;
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IMG_UINT32 ui32Debug;
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IMG_UINT32 ui32DEPC;
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IMG_UINT32 ui32BadInstr;
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RGX_MIPS_TLB_ENTRY asTLB[RGXMIPSFW_NUMBER_OF_TLB_ENTRIES];
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} RGX_MIPS_STATE;
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typedef struct {
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IMG_UINT32 ui32FaultPageEntryLo;
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IMG_UINT32 ui32BadVAddr;
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IMG_UINT32 ui32EntryLo0;
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IMG_UINT32 ui32EntryLo1;
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} RGX_MIPS_FAULT_DATA;
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#endif /* RGXMIPSFW_ASSEMBLY_CODE */
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#endif /*__RGX_MIPS_H__*/
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