/*************************************************************************/ /*!
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@File
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@Title RGX META definitions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description RGX META helper definitions
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined (__RGX_META_H__)
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#define __RGX_META_H__
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/***** The META HW register definitions in the file are updated manually *****/
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#include "img_defs.h"
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#include "km/rgxdefs_km.h"
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/************************************************************************
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* META registers and MACROS
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************************************************************************/
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#define META_CR_CTRLREG_BASE(T) (0x04800000 + 0x1000*(T))
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#define META_CR_TXPRIVEXT (0x048000E8)
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#define META_CR_TXPRIVEXT_MINIM_EN (0x1<<7)
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#define META_CR_SYSC_JTAG_THREAD (0x04830030)
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#define META_CR_SYSC_JTAG_THREAD_PRIV_EN (0x00000004)
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#define META_CR_PERF_COUNT0 (0x0480FFE0)
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#define META_CR_PERF_COUNT1 (0x0480FFE8)
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#define META_CR_PERF_COUNT_CTRL_SHIFT (28)
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#define META_CR_PERF_COUNT_CTRL_MASK (0xF0000000)
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#define META_CR_PERF_COUNT_CTRL_DCACHEHITS (0x8 << META_CR_PERF_COUNT_CTRL_SHIFT)
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#define META_CR_PERF_COUNT_CTRL_ICACHEHITS (0x9 << META_CR_PERF_COUNT_CTRL_SHIFT)
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#define META_CR_PERF_COUNT_CTRL_ICACHEMISS (0xA << META_CR_PERF_COUNT_CTRL_SHIFT)
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#define META_CR_PERF_COUNT_CTRL_ICORE (0xD << META_CR_PERF_COUNT_CTRL_SHIFT)
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#define META_CR_PERF_COUNT_THR_SHIFT (24)
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#define META_CR_PERF_COUNT_THR_MASK (0x0F000000)
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#define META_CR_PERF_COUNT_THR_0 (0x1 << META_CR_PERF_COUNT_THR_SHIFT)
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#define META_CR_PERF_COUNT_THR_1 (0x2 << META_CR_PERF_COUNT_THR_1)
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#define META_CR_TxVECINT_BHALT (0x04820500)
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#define META_CR_PERF_ICORE0 (0x0480FFD0)
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#define META_CR_PERF_ICORE1 (0x0480FFD8)
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#define META_CR_PERF_ICORE_DCACHEMISS (0x8)
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#define META_CR_PERF_COUNT(CTRL, THR) ((META_CR_PERF_COUNT_CTRL_##CTRL << META_CR_PERF_COUNT_CTRL_SHIFT) | \
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(THR << META_CR_PERF_COUNT_THR_SHIFT))
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#define META_CR_TXUXXRXDT_OFFSET (META_CR_CTRLREG_BASE(0) + 0x0000FFF0)
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#define META_CR_TXUXXRXRQ_OFFSET (META_CR_CTRLREG_BASE(0) + 0x0000FFF8)
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#define META_CR_TXUXXRXRQ_DREADY_BIT (0x80000000) /* Poll for done */
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#define META_CR_TXUXXRXRQ_RDnWR_BIT (0x00010000) /* Set for read */
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#define META_CR_TXUXXRXRQ_TX_S (12)
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#define META_CR_TXUXXRXRQ_RX_S (4)
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#define META_CR_TXUXXRXRQ_UXX_S (0)
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#define META_CR_TXUIN_ID (0x0) /* Internal ctrl regs */
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#define META_CR_TXUD0_ID (0x1) /* Data unit regs */
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#define META_CR_TXUD1_ID (0x2) /* Data unit regs */
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#define META_CR_TXUA0_ID (0x3) /* Address unit regs */
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#define META_CR_TXUA1_ID (0x4) /* Address unit regs */
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#define META_CR_TXUPC_ID (0x5) /* PC registers */
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/* Macros to calculate register access values */
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#define META_CR_CORE_REG(Thr, RegNum, Unit) (((Thr) << META_CR_TXUXXRXRQ_TX_S ) | \
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((RegNum) << META_CR_TXUXXRXRQ_RX_S ) | \
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((Unit) << META_CR_TXUXXRXRQ_UXX_S))
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#define META_CR_THR0_PC META_CR_CORE_REG(0, 0, META_CR_TXUPC_ID)
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#define META_CR_THR0_PCX META_CR_CORE_REG(0, 1, META_CR_TXUPC_ID)
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#define META_CR_THR0_SP META_CR_CORE_REG(0, 0, META_CR_TXUA0_ID)
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#define META_CR_THR1_PC META_CR_CORE_REG(1, 0, META_CR_TXUPC_ID)
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#define META_CR_THR1_PCX META_CR_CORE_REG(1, 1, META_CR_TXUPC_ID)
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#define META_CR_THR1_SP META_CR_CORE_REG(1, 0, META_CR_TXUA0_ID)
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#define SP_ACCESS(Thread) META_CR_CORE_REG(Thread, 0, META_CR_TXUA0_ID)
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#define PC_ACCESS(Thread) META_CR_CORE_REG(Thread, 0, META_CR_TXUPC_ID)
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#define META_CR_COREREG_ENABLE (0x0000000)
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#define META_CR_COREREG_STATUS (0x0000010)
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#define META_CR_COREREG_DEFR (0x00000A0)
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#define META_CR_COREREG_PRIVEXT (0x00000E8)
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#define META_CR_T0ENABLE_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_ENABLE)
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#define META_CR_T0STATUS_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_STATUS)
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#define META_CR_T0DEFR_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_DEFR)
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#define META_CR_T0PRIVEXT_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_PRIVEXT)
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#define META_CR_T1ENABLE_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_ENABLE)
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#define META_CR_T1STATUS_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_STATUS)
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#define META_CR_T1DEFR_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_DEFR)
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#define META_CR_T1PRIVEXT_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_PRIVEXT)
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#define META_CR_TXENABLE_ENABLE_BIT (0x00000001) /* Set if running */
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#define META_CR_TXSTATUS_PRIV (0x00020000)
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#define META_CR_TXPRIVEXT_MINIM (0x00000080)
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#define META_MEM_GLOBAL_RANGE_BIT (0x80000000)
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/************************************************************************
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* META LDR Format
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************************************************************************/
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/* Block header structure */
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typedef struct
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{
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IMG_UINT32 ui32DevID;
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IMG_UINT32 ui32SLCode;
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IMG_UINT32 ui32SLData;
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IMG_UINT16 ui16PLCtrl;
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IMG_UINT16 ui16CRC;
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} RGX_META_LDR_BLOCK_HDR;
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/* High level data stream block structure */
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typedef struct
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{
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IMG_UINT16 ui16Cmd;
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IMG_UINT16 ui16Length;
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IMG_UINT32 ui32Next;
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IMG_UINT32 aui32CmdData[4];
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} RGX_META_LDR_L1_DATA_BLK;
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/* High level data stream block structure */
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typedef struct
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{
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IMG_UINT16 ui16Tag;
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IMG_UINT16 ui16Length;
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IMG_UINT32 aui32BlockData[4];
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} RGX_META_LDR_L2_DATA_BLK;
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/* Config command structure */
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typedef struct
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{
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IMG_UINT32 ui32Type;
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IMG_UINT32 aui32BlockData[4];
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} RGX_META_LDR_CFG_BLK;
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/* Block type definitions */
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#define RGX_META_LDR_COMMENT_TYPE_MASK (0x0010)
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#define RGX_META_LDR_BLK_IS_COMMENT(X) ((X & RGX_META_LDR_COMMENT_TYPE_MASK) != 0)
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/* Command definitions
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Value Name Description
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0 LoadMem Load memory with binary data.
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1 LoadCore Load a set of core registers.
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2 LoadMMReg Load a set of memory mapped registers.
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3 StartThreads Set each thread PC and SP, then enable threads.
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4 ZeroMem Zeros a memory region.
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5 Config Perform a configuration command. */
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#define RGX_META_LDR_CMD_MASK (0x000F)
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#define RGX_META_LDR_CMD_LOADMEM (0x0000)
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#define RGX_META_LDR_CMD_LOADCORE (0x0001)
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#define RGX_META_LDR_CMD_LOADMMREG (0x0002)
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#define RGX_META_LDR_CMD_START_THREADS (0x0003)
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#define RGX_META_LDR_CMD_ZEROMEM (0x0004)
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#define RGX_META_LDR_CMD_CONFIG (0x0005)
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/* Config Command definitions
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Value Name Description
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0 Pause Pause for x times 100 instructions
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1 Read Read a value from register - No value return needed.
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Utilises effects of issuing reads to certain registers
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2 Write Write to mem location
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3 MemSet Set mem to value
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4 MemCheck check mem for specific value.*/
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#define RGX_META_LDR_CFG_PAUSE (0x0000)
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#define RGX_META_LDR_CFG_READ (0x0001)
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#define RGX_META_LDR_CFG_WRITE (0x0002)
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#define RGX_META_LDR_CFG_MEMSET (0x0003)
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#define RGX_META_LDR_CFG_MEMCHECK (0x0004)
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/************************************************************************
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* RGX FW segmented MMU definitions
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************************************************************************/
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/* All threads can access the segment */
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#define RGXFW_SEGMMU_ALLTHRS (0xf << 8)
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/* Writable */
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#define RGXFW_SEGMMU_WRITEABLE (0x1 << 1)
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/* All threads can access and writable */
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#define RGXFW_SEGMMU_ALLTHRS_WRITEABLE (RGXFW_SEGMMU_ALLTHRS | RGXFW_SEGMMU_WRITEABLE)
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/* Direct map region 11 used for mapping GPU memory */
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#define RGXFW_SEGMMU_DMAP_GPU_ID (11)
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#define RGXFW_SEGMMU_DMAP_GPU_ADDR_START (0x07800000U)
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/* Segment IDs */
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#define RGXFW_SEGMMU_DATA_ID (1)
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#define RGXFW_SEGMMU_BOOTLDR_ID (2)
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#define RGXFW_SEGMMU_TEXT_ID (RGXFW_SEGMMU_BOOTLDR_ID)
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#define RGXFW_SEGMMU_META_DM_ID (0x7)
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#if defined(HW_ERN_45914)
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/* SLC caching strategy is emitted through the segment MMU. All the segments configured
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through this macro are CACHED in the SLC. The interface has been kept the same to
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simplify the code changes. The bifdm argument is ignored (no longer relevant). */
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#if defined(HW_ERN_49144)
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7(pers, coheren, mmu_ctx) ( (((IMG_UINT64) ((pers) & 0x3)) << 50) | \
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(((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 42) | \
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(((IMG_UINT64) ((coheren) & 0x1)) << 40) )
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x3, 0x0, mmu_ctx)
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x0, 0x1, mmu_ctx)
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/* Set FW code/data cached in the SLC as default */
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#define RGXFW_SEGMMU_OUTADDR_TOP(mmu_ctx, bifdm) RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx | (bifdm&0x0))
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#else
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7(pers, coheren, mmu_ctx) ( (((IMG_UINT64) ((pers) & 0x3)) << 52) | \
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(((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 44) | \
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(((IMG_UINT64) ((coheren) & 0x1)) << 40) )
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x3, 0x0, mmu_ctx)
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#define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x0, 0x1, mmu_ctx)
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/* Set FW code/data cached in the SLC as default */
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#define RGXFW_SEGMMU_OUTADDR_TOP(mmu_ctx, bifdm) RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx | (bifdm&0x0))
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#endif
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#else
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/* To configure the Page Catalog and BIF-DM fed into the BIF for Garten accesses through this segment */
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#define RGXFW_SEGMMU_OUTADDR_TOP(pc, bifdm) ( (((IMG_UINT64) ((pc) & 0xF)) << 44) | \
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(((IMG_UINT64) ((bifdm) & 0xF)) << 40) )
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#endif
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/* META segments have 4kB minimum size */
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#define RGXFW_SEGMMU_ALIGN (0x1000)
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/* Segmented MMU registers (n = segment id) */
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#define META_CR_MMCU_SEGMENTn_BASE(n) (0x04850000 + (n)*0x10)
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#define META_CR_MMCU_SEGMENTn_LIMIT(n) (0x04850004 + (n)*0x10)
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#define META_CR_MMCU_SEGMENTn_OUTA0(n) (0x04850008 + (n)*0x10)
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#define META_CR_MMCU_SEGMENTn_OUTA1(n) (0x0485000C + (n)*0x10)
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/* The following defines must be recalculated if the Meta MMU segments
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* used to access Host-FW data are changed
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* Current combinations are:
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* - SLC uncached, META cached, FW base address 0x70000000
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* - SLC uncached, META uncached, FW base address 0xF0000000
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* - SLC cached, META cached, FW base address 0x10000000
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* - SLC cached, META uncached, FW base address 0x90000000
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*/
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#define RGXFW_SEGMMU_DATA_BASE_ADDRESS (0x10000000)
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#define RGXFW_SEGMMU_DATA_META_CACHED (0x0)
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#define RGXFW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT) // 0x80000000
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#define RGXFW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
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/* For non-VIVT SLCs the cacheability of the FW data in the SLC is selected
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* in the PTEs for the FW data, not in the Meta Segment MMU,
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* which means these defines have no real effect in those cases */
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#define RGXFW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0)
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#define RGXFW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000)
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#define RGXFW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000)
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/************************************************************************
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* RGX FW RGX MMU definitions
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************************************************************************/
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#if defined(RGX_FEATURE_SLC_VIVT) && defined(SUPPORT_TRUSTED_DEVICE)
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#define META_MMU_CONTEXT_MAPPING (0x1) /* fw data */
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#define META_MMU_CONTEXT_MAPPING_CODE (0x0) /* fw code */
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#else
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#define META_MMU_CONTEXT_MAPPING (0x0)
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#endif
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/************************************************************************
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* RGX FW Bootloader defaults
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************************************************************************/
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#define RGXFW_BOOTLDR_META_ADDR (0x40000000)
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#define RGXFW_BOOTLDR_DEVV_ADDR_0 (0xC0000000)
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#define RGXFW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
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#define RGXFW_BOOTLDR_DEVV_ADDR ((((IMG_UINT64) RGXFW_BOOTLDR_DEVV_ADDR_1) << 32) | RGXFW_BOOTLDR_DEVV_ADDR_0)
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#define RGXFW_BOOTLDR_LIMIT (0x1FFFF000)
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/* Bootloader configuration offset is in dwords (512 bytes) */
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#define RGXFW_BOOTLDR_CONF_OFFSET (0x80)
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/************************************************************************
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* RGX META Stack
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************************************************************************/
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#define RGX_META_STACK_SIZE (0x1000)
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/************************************************************************
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* RGX META Core memory
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************************************************************************/
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#if defined(RGXFW_META_SUPPORT_2ND_THREAD)
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#define RGX_META_COREMEM_STACK_SIZE (RGX_META_STACK_SIZE*2)
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#define RGX_META_COREMEM_BSS_SIZE (0xF40)
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#if defined(RGX_FEATURE_META_DMA)
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#define RGX_META_COREMEM_CCBBUF_SIZE (0x2E0)
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#define RGX_META_COREMEM_DATA_SIZE (RGX_META_COREMEM_CCBBUF_SIZE + RGX_META_COREMEM_BSS_SIZE + RGX_META_COREMEM_STACK_SIZE)
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#else
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#define RGX_META_COREMEM_DATA_SIZE (RGX_META_COREMEM_BSS_SIZE + RGX_META_COREMEM_STACK_SIZE)
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#endif
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#else
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#define RGX_META_COREMEM_STACK_SIZE (RGX_META_STACK_SIZE)
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#define RGX_META_COREMEM_BSS_SIZE (0xB00)
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#if defined(RGX_FEATURE_META_DMA)
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#define RGX_META_COREMEM_CCBBUF_SIZE (0x2E0)
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#define RGX_META_COREMEM_DATA_SIZE (RGX_META_COREMEM_CCBBUF_SIZE + RGX_META_COREMEM_BSS_SIZE + RGX_META_COREMEM_STACK_SIZE)
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#else
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#define RGX_META_COREMEM_DATA_SIZE (RGX_META_COREMEM_BSS_SIZE + RGX_META_COREMEM_STACK_SIZE)
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#endif
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#endif
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#if defined (RGX_META_COREMEM_CODE)
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#define RGX_META_COREMEM_CODE_SIZE (RGX_META_COREMEM_SIZE - RGX_META_COREMEM_DATA_SIZE)
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#endif
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/* code and data both map to the same physical memory */
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#define RGX_META_COREMEM_CODE_ADDR (0x80000000)
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#define RGX_META_COREMEM_DATA_ADDR (0x82000000)
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/* because data and code share the same memory, base address for code is offset by the data */
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#define RGX_META_COREMEM_CODE_BADDR (RGX_META_COREMEM_CODE_ADDR + RGX_META_COREMEM_DATA_SIZE)
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#if defined(RGXFW_META_SUPPORT_2ND_THREAD)
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#define RGX_META_COREMEM_STACK_ADDR (RGX_META_COREMEM_DATA_ADDR)
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#define RGX_META_COREMEM_2ND_STACK_ADDR (RGX_META_COREMEM_DATA_ADDR + RGX_META_STACK_SIZE)
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#define RGX_META_COREMEM_BSS_ADDR (RGX_META_COREMEM_2ND_STACK_ADDR + RGX_META_STACK_SIZE)
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#else
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#define RGX_META_COREMEM_STACK_ADDR (RGX_META_COREMEM_DATA_ADDR)
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#define RGX_META_COREMEM_BSS_ADDR (RGX_META_COREMEM_STACK_ADDR + RGX_META_STACK_SIZE)
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#endif
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#if defined(RGX_FEATURE_META_DMA)
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#define RGX_META_COREMEM_CCBBUF_ADDR (RGX_META_COREMEM_BSS_ADDR + RGX_META_COREMEM_BSS_SIZE)
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#endif
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#define RGX_META_IS_COREMEM_CODE(A, B) (((A) >= RGX_META_COREMEM_CODE_ADDR) && ((A) < (RGX_META_COREMEM_CODE_ADDR + (B))))
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#define RGX_META_IS_COREMEM_DATA(A, B) (((A) >= RGX_META_COREMEM_DATA_ADDR) && ((A) < (RGX_META_COREMEM_DATA_ADDR + (B))))
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/************************************************************************
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* 2nd thread
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************************************************************************/
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#define RGXFW_THR1_PC (0x18930000)
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#define RGXFW_THR1_SP (0x78890000)
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/************************************************************************
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* META compatibility
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************************************************************************/
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#define META_CR_CORE_ID (0x04831000)
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#define META_CR_CORE_ID_VER_SHIFT (16U)
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#define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
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#if !defined(__KERNEL__) && defined(RGX_FEATURE_META)
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#if (RGX_FEATURE_META == MTP218)
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#define RGX_CR_META_CORE_ID_VALUE 0x19
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#elif (RGX_FEATURE_META == MTP219)
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#define RGX_CR_META_CORE_ID_VALUE 0x1E
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#elif (RGX_FEATURE_META == LTP218)
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#define RGX_CR_META_CORE_ID_VALUE 0x1C
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#elif (RGX_FEATURE_META == LTP217)
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#define RGX_CR_META_CORE_ID_VALUE 0x1F
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#else
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#error "Unknown META ID"
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#endif
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#else
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#define RGX_CR_META_MTP218_CORE_ID_VALUE 0x19
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#define RGX_CR_META_MTP219_CORE_ID_VALUE 0x1E
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#define RGX_CR_META_LTP218_CORE_ID_VALUE 0x1C
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#define RGX_CR_META_LTP217_CORE_ID_VALUE 0x1F
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#endif
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#define RGXFW_PROCESSOR_META "META"
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#endif /* __RGX_META_H__ */
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/******************************************************************************
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End of file (rgx_meta.h)
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******************************************************************************/
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