/*************************************************************************/ /*!
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@File
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@Title RGX firmware interface structures
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description RGX firmware interface structures shared by both host client
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and host server
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined (__RGX_FWIF_SHARED_H__)
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#define __RGX_FWIF_SHARED_H__
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#if defined(__KERNEL__) && defined(LINUX) && !defined(__GENKSYMS__)
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#define __pvrsrv_defined_struct_enum__
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#include <services_kernel_client.h>
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#endif
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#include "img_types.h"
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#include "rgx_common.h"
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#include "devicemem_typedefs.h"
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/*
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* Firmware binary block unit in bytes.
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* Raw data stored in FW binary will be aligned on this size.
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*/
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#define FW_BLOCK_SIZE 4096L
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/* Offset for BVNC struct from the end of the FW binary */
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#define FW_BVNC_BACKWARDS_OFFSET (FW_BLOCK_SIZE)
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/*!
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******************************************************************************
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* Device state flags
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*****************************************************************************/
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#define RGXKMIF_DEVICE_STATE_ZERO_FREELIST (0x1 << 0) /*!< Zeroing the physical pages of reconstructed free lists */
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#define RGXKMIF_DEVICE_STATE_FTRACE_EN (0x1 << 1) /*!< Used to enable production of GPT FTrace from HWPerf events in the MISR */
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#define RGXKMIF_DEVICE_STATE_DISABLE_DW_LOGGING_EN (0x1 << 2) /*!< Used to disable the Devices Watchdog logging */
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#define RGXKMIF_DEVICE_STATE_DUST_REQUEST_INJECT_EN (0x1 << 3) /*!< Used for validation to inject dust requests every TA/3D kick */
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#define RGXKMIF_DEVICE_STATE_HWPERF_HOST_EN (0x1 << 4) /*!< Used to enable host-side-only HWPerf stream */
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/* Required memory alignment for 64-bit variables accessible by Meta
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(the gcc meta aligns 64-bit vars to 64-bit; therefore, mem shared between
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the host and meta that contains 64-bit vars has to maintain this aligment)*/
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#define RGXFWIF_FWALLOC_ALIGN sizeof(IMG_UINT64)
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typedef struct _RGXFWIF_DEV_VIRTADDR_
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{
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IMG_UINT32 ui32Addr;
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} RGXFWIF_DEV_VIRTADDR;
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typedef struct _RGXFWIF_DMA_ADDR_
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{
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IMG_DEV_VIRTADDR RGXFW_ALIGN psDevVirtAddr;
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RGXFWIF_DEV_VIRTADDR pbyFWAddr;
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} UNCACHED_ALIGN RGXFWIF_DMA_ADDR;
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typedef IMG_UINT8 RGXFWIF_CCCB;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCCB;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCCB_CTL;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RENDER_TARGET;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_HWRTDATA;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_FREELIST;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RAY_FRAME_DATA;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RPM_FREELIST;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RTA_CTL;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_UFO_ADDR;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CLEANUP_CTL;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_TIMESTAMP_ADDR;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_WORKLOAD_DATA;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_DEADLINE_LIST_NODE;
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typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_WORKLOAD_LIST_NODE;
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/* FIXME PRGXFWIF_UFO_ADDR and RGXFWIF_UFO should move back into rgx_fwif_client.h */
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typedef struct _RGXFWIF_UFO_
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{
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PRGXFWIF_UFO_ADDR puiAddrUFO;
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IMG_UINT32 ui32Value;
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} RGXFWIF_UFO;
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/*!
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Last reset reason for a context.
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*/
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typedef enum _RGXFWIF_CONTEXT_RESET_REASON_
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{
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RGXFWIF_CONTEXT_RESET_REASON_NONE = 0, /*!< No reset reason recorded */
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RGXFWIF_CONTEXT_RESET_REASON_GUILTY_LOCKUP = 1, /*!< Caused a reset due to locking up */
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RGXFWIF_CONTEXT_RESET_REASON_INNOCENT_LOCKUP = 2, /*!< Affected by another context locking up */
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RGXFWIF_CONTEXT_RESET_REASON_GUILTY_OVERRUNING = 3, /*!< Overran the global deadline */
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RGXFWIF_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, /*!< Affected by another context overrunning */
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} RGXFWIF_CONTEXT_RESET_REASON;
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/*!
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HWRTData state the render is in
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*/
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typedef enum
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{
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RGXFWIF_RTDATA_STATE_NONE = 0,
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RGXFWIF_RTDATA_STATE_KICKTA,
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RGXFWIF_RTDATA_STATE_KICKTAFIRST,
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RGXFWIF_RTDATA_STATE_TAFINISHED,
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RGXFWIF_RTDATA_STATE_KICK3D,
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RGXFWIF_RTDATA_STATE_3DFINISHED,
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RGXFWIF_RTDATA_STATE_TAOUTOFMEM,
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RGXFWIF_RTDATA_STATE_PARTIALRENDERFINISHED,
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RGXFWIF_RTDATA_STATE_HWR /*!< In case of HWR, we can't set the RTDATA state to NONE,
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as this will cause any TA to become a first TA.
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To ensure all related TA's are skipped, we use the HWR state */
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} RGXFWIF_RTDATA_STATE;
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typedef struct _RGXFWIF_CLEANUP_CTL_
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{
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IMG_UINT32 ui32SubmittedCommands; /*!< Number of commands received by the FW */
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IMG_UINT32 ui32ExecutedCommands; /*!< Number of commands executed by the FW */
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} UNCACHED_ALIGN RGXFWIF_CLEANUP_CTL;
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/*!
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******************************************************************************
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* Client CCB control for RGX
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*****************************************************************************/
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typedef struct _RGXFWIF_CCCB_CTL_
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{
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IMG_UINT32 ui32WriteOffset; /*!< write offset into array of commands (MUST be aligned to 16 bytes!) */
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IMG_UINT32 ui32ReadOffset; /*!< read offset into array of commands */
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IMG_UINT32 ui32DepOffset; /*!< Dependency offset */
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IMG_UINT32 ui32WrapMask; /*!< Offset wrapping mask (Total capacity of the CCB - 1) */
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} UNCACHED_ALIGN RGXFWIF_CCCB_CTL;
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typedef enum
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{
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RGXFW_LOCAL_FREELIST = 0,
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RGXFW_GLOBAL_FREELIST = 1,
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#if defined(SUPPORT_MMU_FREELIST)
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RGXFW_MMU_FREELIST = 2,
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#endif
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RGXFW_MAX_FREELISTS
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} RGXFW_FREELIST_TYPE;
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typedef struct _RGXFWIF_RTA_CTL_
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{
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IMG_UINT32 ui32RenderTargetIndex; //Render number
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IMG_UINT32 ui32CurrentRenderTarget; //index in RTA
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IMG_UINT32 ui32ActiveRenderTargets; //total active RTs
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IMG_UINT32 ui32CumulActiveRenderTargets; //total active RTs from the first TA kick, for OOM
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RGXFWIF_DEV_VIRTADDR sValidRenderTargets; //Array of valid RT indices
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RGXFWIF_DEV_VIRTADDR sNumRenders; //Array of number of occurred partial renders per render target
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IMG_UINT16 ui16MaxRTs; //Number of render targets in the array
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} UNCACHED_ALIGN RGXFWIF_RTA_CTL;
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typedef struct _RGXFWIF_FREELIST_
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{
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IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr;
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IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;
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IMG_UINT32 ui32CurrentStackTop;
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IMG_UINT32 ui32MaxPages;
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IMG_UINT32 ui32GrowPages;
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IMG_UINT32 ui32CurrentPages;
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IMG_UINT32 ui32AllocatedPageCount;
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IMG_UINT32 ui32AllocatedMMUPageCount;
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IMG_UINT32 ui32HWRCounter;
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IMG_UINT32 ui32FreeListID;
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IMG_BOOL bGrowPending;
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} UNCACHED_ALIGN RGXFWIF_FREELIST;
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typedef enum
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{
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RGXFW_RPM_SHF_FREELIST = 0,
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RGXFW_RPM_SHG_FREELIST = 1,
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} RGXFW_RPM_FREELIST_TYPE;
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#define RGXFW_MAX_RPM_FREELISTS (2)
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typedef struct _RGXFWIF_RPM_FREELIST_
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{
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IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListDevVAddr; /*!< device base address */
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//IMG_DEV_VIRTADDR RGXFW_ALIGN sRPMPageListDevVAddr; /*!< device base address for RPM pages in-use */
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IMG_UINT32 sSyncAddr; /*!< Free list sync object for OOM event */
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IMG_UINT32 ui32MaxPages; /*!< maximum size */
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IMG_UINT32 ui32GrowPages; /*!< grow size = maximum pages which may be added later */
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IMG_UINT32 ui32CurrentPages; /*!< number of pages */
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IMG_UINT32 ui32ReadOffset; /*!< head: where to read alloc'd pages */
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IMG_UINT32 ui32WriteOffset; /*!< tail: where to write de-alloc'd pages */
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IMG_BOOL bReadToggle; /*!< toggle bit for circular buffer */
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IMG_BOOL bWriteToggle;
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IMG_UINT32 ui32AllocatedPageCount; /*!< TODO: not sure yet if this is useful */
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IMG_UINT32 ui32HWRCounter;
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IMG_UINT32 ui32FreeListID; /*!< unique ID per device, e.g. rolling counter */
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IMG_BOOL bGrowPending; /*!< FW is waiting for host to grow the freelist */
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} UNCACHED_ALIGN RGXFWIF_RPM_FREELIST;
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typedef struct _RGXFWIF_RAY_FRAME_DATA_
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{
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/* state manager for shared state between vertex and ray processing */
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/* TODO: not sure if this will be useful, link it here for now */
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IMG_UINT32 sRPMFreeLists[RGXFW_MAX_RPM_FREELISTS];
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IMG_BOOL bAbortOccurred;
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/* cleanup state.
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* Both the SHG and RTU must complete or discard any outstanding work
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* which references this frame data.
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*/
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RGXFWIF_CLEANUP_CTL sCleanupStateSHG;
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RGXFWIF_CLEANUP_CTL sCleanupStateRTU;
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IMG_UINT32 ui32CleanupStatus;
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#define HWFRAMEDATA_SHG_CLEAN (1 << 0)
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#define HWFRAMEDATA_RTU_CLEAN (1 << 1)
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} UNCACHED_ALIGN RGXFWIF_RAY_FRAME_DATA;
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typedef struct _RGXFWIF_RENDER_TARGET_
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{
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IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap Data Store */
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IMG_BOOL bTACachesNeedZeroing; /*!< Whether RTC and TPC caches (on mem) need to be zeroed on next first TA kick */
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} UNCACHED_ALIGN RGXFWIF_RENDER_TARGET;
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typedef struct _RGXFWIF_HWRTDATA_
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{
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RGXFWIF_RTDATA_STATE eState;
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IMG_UINT32 ui32NumPartialRenders; /*!< Number of partial renders. Used to setup ZLS bits correctly */
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IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
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IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4];
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IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
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IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4];
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IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
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IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase;
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IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
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#if defined(SUPPORT_VFP)
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IMG_DEV_VIRTADDR RGXFW_ALIGN sVFPPageTableAddr;
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#endif
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IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer;
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IMG_UINT32 ui32PMMListStackPointer;
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PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS];
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IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
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PRGXFWIF_RENDER_TARGET psParentRenderTarget;
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RGXFWIF_CLEANUP_CTL sTACleanupState;
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RGXFWIF_CLEANUP_CTL s3DCleanupState;
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IMG_UINT32 ui32CleanupStatus;
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#define HWRTDATA_TA_CLEAN (1 << 0)
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#define HWRTDATA_3D_CLEAN (1 << 1)
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PRGXFWIF_RTA_CTL psRTACtl;
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IMG_UINT32 bHasLastTA;
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IMG_BOOL bPartialRendered;
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IMG_UINT32 ui32PPPScreen;
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IMG_UINT32 ui32PPPGridOffset;
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IMG_UINT64 RGXFW_ALIGN ui64PPPMultiSampleCtl;
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IMG_UINT32 ui32TPCStride;
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IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr;
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IMG_UINT32 ui32TPCSize;
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IMG_UINT32 ui32TEScreen;
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IMG_UINT32 ui32MTileStride;
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IMG_UINT32 ui32TEAA;
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IMG_UINT32 ui32TEMTILE1;
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IMG_UINT32 ui32TEMTILE2;
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IMG_UINT32 ui32ISPMergeLowerX;
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IMG_UINT32 ui32ISPMergeLowerY;
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IMG_UINT32 ui32ISPMergeUpperX;
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IMG_UINT32 ui32ISPMergeUpperY;
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IMG_UINT32 ui32ISPMergeScaleX;
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IMG_UINT32 ui32ISPMergeScaleY;
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IMG_BOOL bDisableTileReordering;
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} UNCACHED_ALIGN RGXFWIF_HWRTDATA;
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typedef enum
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{
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RGXFWIF_ZSBUFFER_UNBACKED = 0,
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RGXFWIF_ZSBUFFER_BACKED,
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RGXFWIF_ZSBUFFER_BACKING_PENDING,
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RGXFWIF_ZSBUFFER_UNBACKING_PENDING,
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}RGXFWIF_ZSBUFFER_STATE;
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typedef struct _RGXFWIF_ZSBUFFER_
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{
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IMG_UINT32 ui32ZSBufferID; /*!< Buffer ID*/
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IMG_BOOL bOnDemand; /*!< Needs On-demand ZS Buffer allocation */
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RGXFWIF_ZSBUFFER_STATE eState; /*!< Z/S-Buffer state */
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RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
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} UNCACHED_ALIGN RGXFWIF_FWZSBUFFER;
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/* Number of BIF tiling configurations / heaps */
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#define RGXFWIF_NUM_BIF_TILING_CONFIGS 4
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/*!
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*****************************************************************************
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* RGX Compatibility checks
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*****************************************************************************/
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/* WARNING: RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX can be increased only and
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always equal to (N * sizeof(IMG_UINT32) - 1) */
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#define RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX 7
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/* WARNING: Whenever the layout of RGXFWIF_COMPCHECKS_BVNC is a subject of change,
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following define should be increased by 1 to indicate to compatibility logic,
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that layout has changed */
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#define RGXFWIF_COMPCHECKS_LAYOUT_VERSION 2
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typedef struct _RGXFWIF_COMPCHECKS_BVNC_
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{
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IMG_UINT32 ui32LayoutVersion; /* WARNING: This field must be defined as first one in this structure */
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IMG_UINT32 ui32VLenMax;
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IMG_UINT64 RGXFW_ALIGN ui64BNC;
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IMG_CHAR aszV[RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX + 1];
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} UNCACHED_ALIGN RGXFWIF_COMPCHECKS_BVNC;
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#define RGXFWIF_COMPCHECKS_BVNC_DECLARE_AND_INIT(name) \
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RGXFWIF_COMPCHECKS_BVNC name = { \
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RGXFWIF_COMPCHECKS_LAYOUT_VERSION, \
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RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX, \
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0, \
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{ 0 }, \
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}
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#define RGXFWIF_COMPCHECKS_BVNC_INIT(name) \
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do { \
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(name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \
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(name).ui32VLenMax = RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX; \
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(name).ui64BNC = 0; \
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(name).aszV[0] = 0; \
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} while (0)
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typedef struct _RGXFWIF_COMPCHECKS_
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{
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RGXFWIF_COMPCHECKS_BVNC sHWBVNC; /*!< hardware BNC (from the RGX registers) */
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RGXFWIF_COMPCHECKS_BVNC sFWBVNC; /*!< firmware BNC */
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IMG_UINT32 ui32FWProcessorVersion; /*!< identifier of the MIPS/META version */
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IMG_UINT32 ui32DDKVersion; /*!< software DDK version */
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IMG_UINT32 ui32DDKBuild; /*!< software DDK build no. */
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IMG_UINT32 ui32BuildOptions; /*!< build options bit-field */
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IMG_BOOL bUpdated; /*!< Information is valid */
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} UNCACHED_ALIGN RGXFWIF_COMPCHECKS;
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#define GET_CCB_SPACE(WOff, ROff, CCBSize) \
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((((ROff) - (WOff)) + ((CCBSize) - 1)) & ((CCBSize) - 1))
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#define UPDATE_CCB_OFFSET(Off, PacketSize, CCBSize) \
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(Off) = (((Off) + (PacketSize)) & ((CCBSize) - 1))
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#define RESERVED_CCB_SPACE (sizeof(IMG_UINT32))
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/* Defines relating to the per-context CCBs */
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/* This size is to be used when a client CCB is found to consume very negligible space
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* (e.g. a few hundred bytes to few KBs - less than a page). In such a case, instead of
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* allocating CCB of size of only a few KBs, we allocate at-least this much to be future
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* risk-free. */
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#define MIN_SAFE_CCB_SIZE_LOG2 13 /* 8K (2 Pages) */
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/* cCCB sizes per DM context */
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#if defined(EMULATOR)
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/* On emulator platform, the sizes are kept as 64 KB for all contexts as the cCCBs
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* are expected to be almost always used up to their full sizes */
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#define RGX_TQ3D_CCB_SIZE_LOG2 16 /* 64K */
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#define RGX_TQ2D_CCB_SIZE_LOG2 16
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#define RGX_CDM_CCB_SIZE_LOG2 16
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#define RGX_TA_CCB_SIZE_LOG2 16
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#define RGX_3D_CCB_SIZE_LOG2 16
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#define RGX_KICKSYNC_CCB_SIZE_LOG2 16
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#define RGX_RTU_CCB_SIZE_LOG2 16
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#else /* defined (EMULATOR) */
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/* The following figures are obtained by observing the cCCB usage levels of various
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* GL/CL benchmark applications under different platforms and configurations, such
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* that the high watermarks (almost) never hit the full size of the cCCB */
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#define RGX_TQ3D_CCB_SIZE_LOG2 14 /* 16K */
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#define RGX_TQ2D_CCB_SIZE_LOG2 14 /* 16K */
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#define RGX_CDM_CCB_SIZE_LOG2 MIN_SAFE_CCB_SIZE_LOG2 /* The compute cCCB was found to consume only a few hundred bytes on a compute benchmark */
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#define RGX_TA_CCB_SIZE_LOG2 15 /* 32K */
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#define RGX_3D_CCB_SIZE_LOG2 16 /* 64K */
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#define RGX_KICKSYNC_CCB_SIZE_LOG2 MIN_SAFE_CCB_SIZE_LOG2 /* KickSync expected to consume low, hence minimum size */
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#define RGX_RTU_CCB_SIZE_LOG2 15
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#endif /* defined (EMULATOR) */
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/*!
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******************************************************************************
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* Client CCB commands for RGX
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*****************************************************************************/
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#define RGX_CCB_TYPE_TASK (1 << 31)
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#define RGX_CCB_FWALLOC_ALIGN(size) (((size) + (RGXFWIF_FWALLOC_ALIGN-1)) & ~(RGXFWIF_FWALLOC_ALIGN - 1))
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typedef enum _RGXFWIF_CCB_CMD_TYPE_
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{
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RGXFWIF_CCB_CMD_TYPE_TA = 201 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_3D = 202 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_CDM = 203 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_TQ_3D = 204 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_TQ_2D = 205 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_3D_PR = 206 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_NULL = 207 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_SHG = 208 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_RTU = 209 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_RTU_FC = 210 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_PRE_TIMESTAMP = 211 | RGX_CCB_TYPE_TASK,
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RGXFWIF_CCB_CMD_TYPE_TQ_TDM = 212 | RGX_CCB_TYPE_TASK,
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/* Leave a gap between CCB specific commands and generic commands */
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RGXFWIF_CCB_CMD_TYPE_FENCE = 213,
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RGXFWIF_CCB_CMD_TYPE_UPDATE = 214,
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RGXFWIF_CCB_CMD_TYPE_RMW_UPDATE = 215,
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RGXFWIF_CCB_CMD_TYPE_FENCE_PR = 216,
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RGXFWIF_CCB_CMD_TYPE_PRIORITY = 217,
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/* Pre and Post timestamp commands are supposed to sandwich the DM cmd. The
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padding code with the CCB wrap upsets the FW if we don't have the task type
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bit cleared for POST_TIMESTAMPs. That's why we have 2 different cmd types.
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*/
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RGXFWIF_CCB_CMD_TYPE_POST_TIMESTAMP = 218,
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RGXFWIF_CCB_CMD_TYPE_UNFENCED_UPDATE = 219,
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RGXFWIF_CCB_CMD_TYPE_UNFENCED_RMW_UPDATE = 220,
|
|
RGXFWIF_CCB_CMD_TYPE_PADDING = 221,
|
} RGXFWIF_CCB_CMD_TYPE;
|
|
typedef struct _RGXFWIF_WORKLOAD_DATA_
|
{
|
/* Workload characteristics data*/
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadCharacteristics;
|
/* Deadline for the workload */
|
IMG_UINT64 RGXFW_ALIGN ui64DeadlineInus;
|
/* Bool for whether the workload was completed */
|
IMG_BOOL bComplete;
|
/* Predicted time taken to do the work in cycles */
|
IMG_UINT64 RGXFW_ALIGN ui64CyclesPrediction;
|
/* The actual time taken in cycles */
|
IMG_UINT64 RGXFW_ALIGN ui64CyclesTaken;
|
/* The memory descriptor for this workload */
|
IMG_UINT64 RGXFW_ALIGN ui64SelfMemDesc;
|
/* Memory descriptor to be able to chain workload data */
|
IMG_UINT64 RGXFW_ALIGN ui64NextNodeMemdesc;
|
/* Reference to Host side data */
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadHostData;
|
/* Reference to Specific Hash table */
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadMatchingData;
|
/* The following are for the memory management of the PDVFS workload
|
* tree in the firmware */
|
PRGXFWIF_DEADLINE_LIST_NODE RGXFW_ALIGN sDeadlineNodeFWAddress;
|
PRGXFWIF_WORKLOAD_LIST_NODE RGXFW_ALIGN sWorkloadNodeFWAddress;
|
IMG_UINT64 RGXFW_ALIGN ui64DeadlineNodeMemDesc;
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadNodeMemDesc;
|
} RGXFWIF_WORKLOAD_DATA;
|
|
typedef struct _RGXFWIF_WORKEST_KICK_DATA_
|
{
|
/* Index for the KM Workload estimation return data array */
|
IMG_UINT64 RGXFW_ALIGN ui64ReturnDataIndex;
|
/* Deadline for the workload */
|
IMG_UINT64 RGXFW_ALIGN ui64DeadlineInus;
|
/* Predicted time taken to do the work in cycles */
|
IMG_UINT64 RGXFW_ALIGN ui64CyclesPrediction;
|
} RGXFWIF_WORKEST_KICK_DATA;
|
|
typedef struct _RGXFWIF_WORKLOAD_LIST_NODE_ RGXFWIF_WORKLOAD_LIST_NODE;
|
typedef struct _RGXFWIF_DEADLINE_LIST_NODE_ RGXFWIF_DEADLINE_LIST_NODE;
|
|
struct _RGXFWIF_WORKLOAD_LIST_NODE_
|
{
|
IMG_UINT64 RGXFW_ALIGN ui64Cycles;
|
IMG_UINT64 RGXFW_ALIGN ui64SelfMemDesc;
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadDataMemDesc;
|
IMG_BOOL bReleased;
|
RGXFWIF_WORKLOAD_LIST_NODE *psNextNode;
|
};
|
|
struct _RGXFWIF_DEADLINE_LIST_NODE_
|
{
|
IMG_UINT64 RGXFW_ALIGN ui64DeadlineInus;
|
RGXFWIF_WORKLOAD_LIST_NODE *psWorkloadList;
|
IMG_UINT64 RGXFW_ALIGN ui64SelfMemDesc;
|
IMG_UINT64 RGXFW_ALIGN ui64WorkloadDataMemDesc;
|
IMG_BOOL bReleased;
|
RGXFWIF_DEADLINE_LIST_NODE *psNextNode;
|
};
|
typedef struct _RGXFWIF_CCB_CMD_HEADER_
|
{
|
RGXFWIF_CCB_CMD_TYPE eCmdType;
|
IMG_UINT32 ui32CmdSize;
|
IMG_UINT32 ui32ExtJobRef; /*!< external job reference - provided by client and used in debug for tracking submitted work */
|
IMG_UINT32 ui32IntJobRef; /*!< internal job reference - generated by services and used in debug for tracking submitted work */
|
PRGXFWIF_WORKLOAD_DATA RGXFW_ALIGN sWorkloadDataFWAddr;
|
RGXFWIF_WORKEST_KICK_DATA sWorkEstKickData; /*!< Workload Estimation - Workload Estimation Data */
|
} RGXFWIF_CCB_CMD_HEADER;
|
|
typedef enum _RGXFWIF_REG_CFG_TYPE_
|
{
|
RGXFWIF_REG_CFG_TYPE_PWR_ON=0, /* Sidekick power event */
|
RGXFWIF_REG_CFG_TYPE_DUST_CHANGE, /* Rascal / dust power event */
|
RGXFWIF_REG_CFG_TYPE_TA, /* TA kick */
|
RGXFWIF_REG_CFG_TYPE_3D, /* 3D kick */
|
RGXFWIF_REG_CFG_TYPE_CDM, /* Compute kick */
|
RGXFWIF_REG_CFG_TYPE_TLA, /* TLA kick */
|
RGXFWIF_REG_CFG_TYPE_TDM, /* TDM kick */
|
RGXFWIF_REG_CFG_TYPE_ALL /* Applies to all types. Keep as last element */
|
} RGXFWIF_REG_CFG_TYPE;
|
|
typedef struct _RGXFWIF_REG_CFG_REC_
|
{
|
IMG_UINT64 ui64Addr;
|
IMG_UINT64 ui64Mask;
|
IMG_UINT64 ui64Value;
|
} RGXFWIF_REG_CFG_REC;
|
|
|
typedef struct _RGXFWIF_TIME_CORR_
|
{
|
IMG_UINT64 RGXFW_ALIGN ui64OSTimeStamp;
|
IMG_UINT64 RGXFW_ALIGN ui64OSMonoTimeStamp;
|
IMG_UINT64 RGXFW_ALIGN ui64CRTimeStamp;
|
IMG_UINT32 ui32CoreClockSpeed;
|
|
/* Utility variable used to convert CR timer deltas to OS timer deltas (nS),
|
* where the deltas are relative to the timestamps above:
|
* deltaOS = (deltaCR * K) >> decimal_shift, see full explanation below */
|
IMG_UINT32 ui32CRDeltaToOSDeltaKNs;
|
} UNCACHED_ALIGN RGXFWIF_TIME_CORR;
|
|
|
/* These macros are used to help converting FW timestamps to the Host time domain.
|
* On the FW the RGX_CR_TIMER counter is used to keep track of the time;
|
* it increments by 1 every 256 GPU clock ticks, so the general formula
|
* to perform the conversion is:
|
*
|
* [ GPU clock speed in Hz, if (scale == 10^9) then deltaOS is in nS,
|
* otherwise if (scale == 10^6) then deltaOS is in uS ]
|
*
|
* deltaCR * 256 256 * scale
|
* deltaOS = --------------- * scale = deltaCR * K [ K = --------------- ]
|
* GPUclockspeed GPUclockspeed
|
*
|
* The actual K is multiplied by 2^20 (and deltaCR * K is divided by 2^20)
|
* to get some better accuracy and to avoid returning 0 in the integer
|
* division 256000000/GPUfreq if GPUfreq is greater than 256MHz.
|
* This is the same as keeping K as a decimal number.
|
*
|
* The maximum deltaOS is slightly more than 5hrs for all GPU frequencies
|
* (deltaCR * K is more or less a constant), and it's relative to
|
* the base OS timestamp sampled as a part of the timer correlation data.
|
* This base is refreshed on GPU power-on, DVFS transition and
|
* periodic frequency calibration (executed every few seconds if the FW is
|
* doing some work), so as long as the GPU is doing something and one of these
|
* events is triggered then deltaCR * K will not overflow and deltaOS will be
|
* correct.
|
*/
|
|
#define RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT (20)
|
|
#define RGXFWIF_GET_CRDELTA_TO_OSDELTA_K_NS(clockfreq, remainder) \
|
OSDivide64((256000000ULL << RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT), \
|
((clockfreq) + 500) / 1000, \
|
&(remainder))
|
|
#define RGXFWIF_GET_DELTA_OSTIME_NS(deltaCR, K) \
|
( ((deltaCR) * (K)) >> RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT)
|
|
#define RGXFWIF_GET_DELTA_OSTIME_US(deltacr, clockfreq, remainder) \
|
OSDivide64r64((deltacr) * 256000, ((clockfreq) + 500) / 1000, &(remainder))
|
|
/* Use this macro to get a more realistic GPU core clock speed than
|
* the one given by the upper layers (used when doing GPU frequency
|
* calibration)
|
*/
|
#define RGXFWIF_GET_GPU_CLOCK_FREQUENCY_HZ(deltacr_us, deltaos_us, remainder) \
|
OSDivide64((deltacr_us) * 256000000, (deltaos_us), &(remainder))
|
|
/*
|
The maximum configurable size via RGX_FW_HEAP_SHIFT is
|
32MiB (1<<25) and the minimum is 4MiB (1<<22); the
|
default firmware heap size is set to maximum 32MiB.
|
*/
|
#if (RGX_FW_HEAP_SHIFT < 22 || RGX_FW_HEAP_SHIFT > 25)
|
#error "RGX_FW_HEAP_SHIFT is outside valid range [22, 25]"
|
#endif
|
|
#endif /* __RGX_FWIF_SHARED_H__ */
|
|
/******************************************************************************
|
End of file (rgx_fwif_shared.h)
|
******************************************************************************/
|
